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A Compiler for Compiler 2018 Course at ACM Class, SJTU
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
C++ program that simulates five stage pipeline to process MIPS instructions, course project of PPCA 2017, ACM Class, SJTU.
Lecture notes of Computer Architecture course, ACM Class, SJTU.
Python scripts to extend functions of personal WeChat accounts, using itchat. / 扩展个人微信账号功能的Python脚本，使用开源的WeChat的Python接口itchat。
AI program of Chinese Battle chess, course project of Programming 2016, ACM Class, SJTU.
524 contributions in the last year
in private repositories
Oct 1 – Oct 17
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