clock generator (saft-clk-gen) has strange phase offset

[dietrichb]

when generating clocks at a TR using saft-clk-gen the generated clock signals have a phase offset of about 625 ns (expected value is 0ns).

As an example, this can be observed when generating a 1 Hz clock

[dietrichb]

eb-info dev/wbm0:

1879cee microtca: changed fitter seed
d3b3258 pmc: changed fitter seed
ec83a75 ftm: changed fitter seed
a88b671 pexarria5: changed fitter seed
11d4f7a exploder5: changed fitter seed

[alyxazon]

Fixed, see syn/common)/arria5_serdes_lvds_patch.tcl.