7) Description of Design

• A description of your design in a form that people who aren’t familiar with the work can understand how the design was achieved. Imagine one of your classmates was to use your project and extend it. What would they need to know about how you built your project

The first part of the design was the size of the system, the size of our system was chosen to be 16 bits, this is less than the usual 32, but since we were just figuring things out we decided to start small. The first stage of the design of the MIPS processor was to create an arithmetic unit that would be able to handle what the demand of the 16 bit instruction file. As well as the various commands and instructions that would be sent to it.
The next stage was to work on the register files, make them so we could store the results from an r type instruction properly. This requires multiplexers to read the address that is included in the instruction. We used a type of pseudo-memory to save the bits that were created instead of memory.
The processor uses the built in clock to determine when to do each stage, some were done at the same time. It also implements what is called a program counter or PC to maintain a storage of where the processor is in the memory being read. This is based off of where the processor is, meaning what state in the finite state machine aspect. The PC is incremented after every step, or increment that a bit goes through, focused on the slowest step in the processor.
The whole system was compiled as a finite state machine where the each of the steps could be executed. The state transitions were mostly controlled by the value of a counter tracking the number of clock cycles. The FSM would make complete cycle of the states every 20 clock cycles.

##Instruction breakdown

opcode; this defines what type of instruction it is
rs; this is the register that is supplying the information
rt; this is the second source register (R-Type), or the destination register
rd; this is the destination register for R-Type instructions shamt; this is the shift amount, or how much a register needs to be shifted
function; this determines which operation is to be performed
immediate; this is used to locate where to load data from or store data to memory address; this is used to set where a set of memory will be going

The layout of an R type is as follows;
4- opcode
2- rs
2- rt
2-rd
2-shamt
2-funct

They layout of a load and store and i type instructions looks like;
4-opcode
2-rs
2-rt
8-immediate

The breakdown of jump instructions goes like this;
4-opcode
12-address

##Components 8 Registers

• 3 general registers (A,B,C) with the following identifiers for rs, rt, and rd:
• • A = 01
• • B = 10
• • C = 11
• • Note: See zero-dedicated register for 00 identifier
• 5 special purpose registers
• • zero-dedicated register (always has the value zero.) with the identifier 00
• • Instruction register (IR)
• • Memory Address register (MAR)
• • Memory Data register (MDR)
• • ALU output register (holds the output of the ALU)

An ALU

• In the current version only addition, subtraction, bitwise AND, bitwise OR are valid operations. However, it takes a 3-bit operation signal, and so can be extended to 8 total operations. Future operations to add (if I have the time to play around with this later) will most likely be logical shifts, greater than and less than. Also, an output signal for equal to and not equal to comparisons could be added (i.e. zero_signal = A-B ? 1 : 0;)

Main Control Unit

• This was the top-level module and is further elaborated upon in Description of Design (Control)

Main Memory

• started with memory-like module
• • This module acted like memory, but not exactly. It had only 16 addresses with one address every 4 bits with nothing in between. Addresses 0-32 corresponded to the instructions to be executed (hard-coded in), while addresses 36-56 held data values and addresses 60 and 64 held constants. It also had a default "no-operation/zero-value" address if the address input did not actually exist.
• goal was on board sRAM (unsuccessful)