8.) Description of Design (Control)

#Overview The top level module in our design was the control design. It was here that are data path was determined and control signals were set.

We started the control unit as a 5 state finite state machine, with each state corresponding to one of the stages in the MIPS datapath (IF, ID, EX, MA, and WB). We later expanded it to 9 states, essentially subdividing the ID stage into 4 stages: One for R-Type instructions, one for Load instructions, one for Store instructions, and one for Branch instructions. Finally, we changed the design so that the processor would stay in each state long enough for to ensure the signal propagated through everywhere it needed to. We did this by introducing a count of the number of clock cycles passed and advancing through the states based on this counter. This then prompted a 10th state to reset the clock cycle count which we also used to ensure that all control signals were reset before fetching the next instruction. In the present design we allowed 2x the number of clock cycles to elapse before proceeding to the next state.

#Breakdown of States

Instruction Fetch (IF)

At the beginning of this stage the MAR takes the address from the PC while the memory write-enable signal is set to LOW to ensure that the MDR receives the instruction and does not write over the instruction. The MDR then passes the instruction to the IR for use in the next stage, ID. At the end of this stage all enable signals are set LOW and the PC is incremented by 4 (decimal).

Instruction Decode (ID)

In this stage the instruction is broken up into the opcode, rs, rt, rd, shamt, funct, and address values. The next stage is dependent upon the value of the opcode. The current design has the following definitions for the opcode:

• R-Type: opcode = 0
• Load: opcode = 8
• Store: opcode = 12
• Branch: opcode = 4

R-Type Instructions (R_TYPE)

In this stage the two source registers are determined by rs and rt. The destination register is determined by rd, and the operation for the ALU is determined by funct. In the current design, shamt is irrelevant as the ALU does not perform shift operations. The RegDst signal is set HIGH so that the destination register will use rd. RegWrite is set HIGH so that writing back to a Register is enabled. All other signals are LOW.

Load Instructions (LOAD)

In this stage the zero register is typically selected by rs (though nothing prevents a different register from being selected) for source 1 of the ALU. While source 2 will be the address value sign extended to 16 bits, it is not currently implemented. The destination register is determined by rt since RegDst is set LOW. ALUSrc is set HIGH so that the sign extended address is used for source 2 and RegWrite is set HIGH also. All other signals are LOW.

Store Instructions (STORE)

In this stage rs is once again typically the zero register. ALU once again uses the sign extended address for source 2 (ALUSrc = HIGH). The memory write signal, wren, is set HIGH so that the value from register selected by rt will be written to the appropriate address.

Branch Instructions (BRANCH)

In this stage only the Branch signal will be set HIGH. If the comparison between the registers selected by rs and rt (rs-rt) is correct, then the PC will be incremented by the sign extended address value, shifted left by 2. In the current design, this is not complete, but the intent was going to be for a branch equals instruction, in which case it will branch when rs-rt = 0.

Execute (EX)

In the beginning of this stage, the ALU dedicated register is set to accepted the ALU output. At the end of the stage is disabled.

Memory Access (MA)

In this stage, for R-Type and Branch instructions, nothing occurs (this stage passes by with no change in values). While not implemented in the current design, for Load instructions the address computed by the LAU and sent to the MAR, that address will be read and the value stored in MDR. For Store type instructions, the data from register determined by rt will be accepted by MDR while the address computed by the ALU will be stored in MAR.

Write Back (WB)

In the current design, only the R-Type instructions will work. Here, the rd registers write enable signal is set to HIGH, and the value computed by the ALU is written to it.

Reset Counter (RST_CYCLES)

In this stage, the cycles value is reset and all signals are set low to prepare for the next instruction.