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PREFACE

This thesis was developed as a result of multiple projects I have accomplished at the University of New Hampshire (UNH). The accumulated experience enabled me to compose the foundation and formalisms of an enhanced design framework presented in this thesis. The projects are as follows:

  • Developed a complete set of nine Texas Instruments (Tl) laboratory experiments introducing designers to fast in-house complex digital system development (Refer to Appendices C-K). The laboratories have been published in a TI book "Introduction to FPGA-Based Microsystem Design" [RuHl93].

  • Implemented an 8-bit parallel-to-serial and serial-to-parallel converter for the National Aeronautics and Space Agency's (NASAs) rocket project using a CMOS standard-cell, very large scale integration (VLSI) process. This application specific integrated circuit (ASIC), also known as the Aydin Vector Serial/Parallel Interface (AVSPI), is part of a larger system which is used to gather gamma ray information in the upper atmosphere. The system is currently used on board rockets and will eventually be placed in a NASA satellite [Deco91a].

  • Built a stand-alone speaker dependent speech recognition system using TIs TMS320 digital signal processing (DSP) chip and standard parts in a real­time environment [Deco91b].

  • Used the description tool VHDL to model, simulate and synthesize a programmable 8-bit microprocessor for implementation with a Xilinx field programmable gate array (FPGA). The system is capable of decoding a small instruction set and was based on a standard part implementation [SeFi91]. It was completely modeled in structural VHDL code, written specifically for an FPGA using hard and soft macros (Refer to Appendix L) [Deco92].

  • Analyzed the Mentor Graphics electronic design automation (EDA) environment, a collection of tools built around the Falcon Framework. The design environment provides VHDL EDA tools as well as multichip module (MCM) development capabilities [Ment92] [Ment91a-f] [Ment90a-b].

  • Attended a one week intensive training session on VHDL logic synthesis at Viewlogic. Various VHDL modeling styles tailored specifically to their synthesis system were examined [View93].