Implement SPV_INTEL_fpga_function_attributes extension

The extension introduces 4 more execution modes: - MaxWorkgroupSizeINTEL: Indicates the maximum possible work-group size in the x, y, and z dimensions. Only valid with the Kernel Execution Model. - MaxWorkDimINTEL: Indicates the maximum number of work dimensions. Legal values range from 0 to 3. A maximum dimensionality of 0 indicates that the kernel can only be launched with a single work-item. Only valid with the Kernel Execution Model. - NoGlobalOffsetINTEL (out of scope of this patch): Indicates that the global offset is always (0, 0, 0). Only valid with the Kernel Execution Model. - NumSIMDWorkitemsINTEL: Indicates that work-items should be vectorized with the provided vector width. Only valid with the Kernel Execution Model. The execution modes are needed to handle the appropriate SYCL kernel attributes. Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
KhronosGroup · Dec 23, 2019 · 9833dca · 9833dca
1 parent 2377924
commit 9833dca
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diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc
@@ -13,3 +13,4 @@ EXT(SPV_INTEL_unstructured_loop_controls)
 EXT(SPV_INTEL_fpga_reg)
 EXT(SPV_INTEL_blocking_pipes)
 EXT(SPV_INTEL_function_pointers)
+EXT(SPV_INTEL_kernel_attributes)
diff --git a/lib/SPIRV/PreprocessMetadata.cpp b/lib/SPIRV/PreprocessMetadata.cpp
@@ -198,6 +198,39 @@ void PreprocessMetadata::visit(Module *M) {
           .add(getMDOperandAsInt(ReqdSubgroupSize, 0))
           .done();
     }
+
+    // !{void (i32 addrspace(1)*)* @kernel, i32 max_work_group_size, i32 X,
+    //         i32 Y, i32 Z}
+    if (MDNode *MaxWorkgroupSizeINTEL =
+            Kernel.getMetadata(kSPIR2MD::MaxWGSize)) {
+      unsigned X, Y, Z;
+      decodeMDNode(MaxWorkgroupSizeINTEL, X, Y, Z);
+      EM.addOp()
+          .add(&Kernel)
+          .add(spv::ExecutionModeMaxWorkgroupSizeINTEL)
+          .add(X)
+          .add(Y)
+          .add(Z)
+          .done();
+    }
+
+    // !{void (i32 addrspace(1)*)* @kernel, i32 max_global_work_dim, i32 dim}
+    if (MDNode *MaxWorkDimINTEL = Kernel.getMetadata(kSPIR2MD::MaxWGDim)) {
+      EM.addOp()
+          .add(&Kernel)
+          .add(spv::ExecutionModeMaxWorkDimINTEL)
+          .add(getMDOperandAsInt(MaxWorkDimINTEL, 0))
+          .done();
+    }
+
+    // !{void (i32 addrspace(1)*)* @kernel, i32 num_simd_work_items, i32 num}
+    if (MDNode *NumSIMDWorkitemsINTEL = Kernel.getMetadata(kSPIR2MD::NumSIMD)) {
+      EM.addOp()
+          .add(&Kernel)
+          .add(spv::ExecutionModeNumSIMDWorkitemsINTEL)
+          .add(getMDOperandAsInt(NumSIMDWorkitemsINTEL, 0))
+          .done();
+    }
   }
 }
 

diff --git a/lib/SPIRV/SPIRVInternal.h b/lib/SPIRV/SPIRVInternal.h
@@ -375,6 +375,9 @@ const static char VecTyHint[] = "vec_type_hint";
 const static char WGSize[] = "reqd_work_group_size";
 const static char WGSizeHint[] = "work_group_size_hint";
 const static char SubgroupSize[] = "intel_reqd_sub_group_size";
+const static char MaxWGSize[] = "max_work_group_size";
+const static char MaxWGDim[] = "max_global_work_dim";
+const static char NumSIMD[] = "num_simd_work_items";
 } // namespace kSPIR2MD
 
 enum Spir2SamplerKind {

diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp
@@ -3146,6 +3146,21 @@ bool SPIRVToLLVM::transKernelMetadata() {
       auto SizeMD = ConstantAsMetadata::get(getUInt32(M, EM->getLiterals()[0]));
       F->setMetadata(kSPIR2MD::SubgroupSize, MDNode::get(*Context, SizeMD));
     }
+    // Generate metadata for max_work_group_size
+    if (auto EM = BF->getExecutionMode(ExecutionModeMaxWorkgroupSizeINTEL)) {
+      F->setMetadata(kSPIR2MD::MaxWGSize,
+                     getMDNodeStringIntVec(Context, EM->getLiterals()));
+    }
+    // Generate metadata for max_global_work_dim
+    if (auto EM = BF->getExecutionMode(ExecutionModeMaxWorkDimINTEL)) {
+      F->setMetadata(kSPIR2MD::MaxWGDim,
+                     getMDNodeStringIntVec(Context, EM->getLiterals()));
+    }
+    // Generate metadata for num_simd_work_items
+    if (auto EM = BF->getExecutionMode(ExecutionModeNumSIMDWorkitemsINTEL)) {
+      F->setMetadata(kSPIR2MD::NumSIMD,
+                     getMDNodeStringIntVec(Context, EM->getLiterals()));
+    }
   }
   return true;
 }

diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp
@@ -1881,6 +1881,16 @@ bool LLVMToSPIRV::transExecutionMode() {
         BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
             BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
       } break;
+      case spv::ExecutionModeMaxWorkgroupSizeINTEL: {
+        if (BM->isAllowedToUseExtension(
+                ExtensionID::SPV_INTEL_kernel_attributes)) {
+          unsigned X, Y, Z;
+          N.get(X).get(Y).get(Z);
+          BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
+              BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
+          BM->addCapability(CapabilityKernelAttributesINTEL);
+        }
+      } break;
       case spv::ExecutionModeVecTypeHint:
       case spv::ExecutionModeSubgroupSize:
       case spv::ExecutionModeSubgroupsPerWorkgroup: {
@@ -1889,6 +1899,26 @@ bool LLVMToSPIRV::transExecutionMode() {
         BF->addExecutionMode(BM->add(
             new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode), X)));
       } break;
+      case spv::ExecutionModeNumSIMDWorkitemsINTEL: {
+        if (BM->isAllowedToUseExtension(
+                ExtensionID::SPV_INTEL_kernel_attributes)) {
+          unsigned X;
+          N.get(X);
+          BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
+              BF, static_cast<ExecutionMode>(EMode), X)));
+          BM->addCapability(CapabilityFPGAKernelAttributesINTEL);
+        }
+      } break;
+      case spv::ExecutionModeMaxWorkDimINTEL: {
+        if (BM->isAllowedToUseExtension(
+                ExtensionID::SPV_INTEL_kernel_attributes)) {
+          unsigned X;
+          N.get(X);
+          BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
+              BF, static_cast<ExecutionMode>(EMode), X)));
+          BM->addCapability(CapabilityFPGAKernelAttributesINTEL);
+        }
+      } break;
       default:
         llvm_unreachable("invalid execution mode");
       }

diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.cpp b/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
@@ -456,12 +456,15 @@ void SPIRVExecutionMode::decode(std::istream &I) {
   switch (ExecMode) {
   case ExecutionModeLocalSize:
   case ExecutionModeLocalSizeHint:
+  case ExecutionModeMaxWorkgroupSizeINTEL:
     WordLiterals.resize(3);
     break;
   case ExecutionModeInvocations:
   case ExecutionModeOutputVertices:
   case ExecutionModeVecTypeHint:
   case ExecutionModeSubgroupSize:
+  case ExecutionModeMaxWorkDimINTEL:
+  case ExecutionModeNumSIMDWorkitemsINTEL:
     WordLiterals.resize(1);
     break;
   default:

diff --git a/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
@@ -140,6 +140,9 @@ inline bool isValid(spv::ExecutionMode V) {
   case ExecutionModeFinalizer:
   case ExecutionModeSubgroupSize:
   case ExecutionModeSubgroupsPerWorkgroup:
+  case ExecutionModeMaxWorkgroupSizeINTEL:
+  case ExecutionModeMaxWorkDimINTEL:
+  case ExecutionModeNumSIMDWorkitemsINTEL:
     return true;
   default:
     return false;
@@ -561,6 +564,8 @@ inline bool isValid(spv::Capability V) {
   case CapabilityFPGALoopControlsINTEL:
   case CapabilityBlockingPipesINTEL:
   case CapabilityUnstructuredLoopControlsINTEL:
+  case CapabilityKernelAttributesINTEL:
+  case CapabilityFPGAKernelAttributesINTEL:
     return true;
   default:
     return false;

diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
@@ -119,6 +119,9 @@ template <> inline void SPIRVMap<ExecutionMode, std::string>::init() {
   add(ExecutionModeOutputTriangleStrip, "OutputTriangleStrip");
   add(ExecutionModeVecTypeHint, "VecTypeHint");
   add(ExecutionModeContractionOff, "ContractionOff");
+  add(ExecutionModeMaxWorkgroupSizeINTEL, "MaxWorkgroupSizeINTEL");
+  add(ExecutionModeMaxWorkDimINTEL, "MaxWorkDimINTEL");
+  add(ExecutionModeNumSIMDWorkitemsINTEL, "NumSIMDWorkitemsINTEL");
 }
 SPIRV_DEF_NAMEMAP(ExecutionMode, SPIRVExecutionModeNameMap)
 
@@ -495,6 +498,8 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
   add(CapabilityUnstructuredLoopControlsINTEL, "UnstructuredLoopControlsINTEL");
   add(CapabilityFunctionPointersINTEL, "FunctionPointersINTEL");
   add(CapabilityIndirectReferencesINTEL, "IndirectReferencesINTEL");
+  add(CapabilityKernelAttributesINTEL, "KernelAttributesINTEL");
+  add(CapabilityFPGAKernelAttributesINTEL, "FPGAKernelAttributesINTEL");
 }
 SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
 

diff --git a/lib/SPIRV/libSPIRV/spirv.hpp b/lib/SPIRV/libSPIRV/spirv.hpp
@@ -126,6 +126,10 @@ enum ExecutionMode {
     ExecutionModeFinalizer = 34,
     ExecutionModeSubgroupSize = 35,
     ExecutionModeSubgroupsPerWorkgroup = 36,
+    ExecutionModeMaxWorkgroupSizeINTEL = 5893,
+    ExecutionModeMaxWorkDimINTEL = 5894,
+    ExecutionModeNoGlobalOffsetINTEL = 5895,
+    ExecutionModeNumSIMDWorkitemsINTEL = 5896,
     ExecutionModeMax = 0x7fffffff,
 };
 
@@ -686,6 +690,8 @@ enum Capability {
   CapabilityFPGALoopControlsINTEL = 5888,
   CapabilityBlockingPipesINTEL = 5945,
   CapabilityFPGARegINTEL = 5948,
+  CapabilityKernelAttributesINTEL= 5892,
+  CapabilityFPGAKernelAttributesINTEL= 5897,
   CapabilityMax = 0x7fffffff,
 };
 

diff --git a/test/IntelFPGAFunctionAttributes.ll b/test/IntelFPGAFunctionAttributes.ll
@@ -0,0 +1,100 @@
+;; Can be compiled using https://github.com/intel/llvm SYCL compiler from:
+;; class Foo {
+;; public:
+;;   [[intelfpga::max_global_work_dim(1),
+;;     intelfpga::max_work_group_size(1,1,1),
+;;     intelfpga::num_simd_work_items(8)]] void operator()() {}
+;; };
+;;
+;; template <typename name, typename Func>
+;; __attribute__((sycl_kernel)) void kernel(Func kernelFunc) {
+;;   kernelFunc();
+;; }
+;;
+;; void bar() {
+;;   Foo boo;
+;;   kernel<class kernel_name>(boo);
+;; }
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_kernel_attributes -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; RUN: llvm-spirv -spirv-text -r %t.spt -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: 2 Capability KernelAttributesINTEL
+; CHECK-SPIRV: 2 Capability FPGAKernelAttributesINTEL
+; CHECK-SPIRV: 6 ExecutionMode [[FUNCENTRY:[0-9]+]] 5893 1 1 1
+; CHECK-SPIRV: 4 ExecutionMode [[FUNCENTRY]] 5894 1
+; CHECK-SPIRV: 4 ExecutionMode [[FUNCENTRY]] 5896 8
+; CHECK-SPIRV: 5 Function {{.*}} [[FUNCENTRY]] {{.*}}
+
+; CHECK-LLVM: define spir_kernel void {{.*}}kernel_name() {{.*}} !max_work_group_size ![[MAXWG:[0-9]+]] !max_global_work_dim ![[MAXWD:[0-9]+]] !num_simd_work_items ![[NUMSIMD:[0-9]+]]
+; CHECK-LLVM: ![[MAXWG]] = !{i32 1, i32 1, i32 1}
+; CHECK-LLVM: ![[MAXWD]] = !{i32 1}
+; CHECK-LLVM: ![[NUMSIMD]] = !{i32 8}
+
+; ModuleID = 'kernel-attrs.cpp'
+source_filename = "kernel-attrs.cpp"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-linux-sycldevice"
+
+%class._ZTS3Foo.Foo = type { i8 }
+
+$_ZN3FooclEv = comdat any
+
+; Function Attrs: nounwind
+define spir_kernel void @_ZTSZ3barvE11kernel_name() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 !num_simd_work_items !5 !max_work_group_size !6 !max_global_work_dim !7 {
+entry:
+  %Foo = alloca %class._ZTS3Foo.Foo, align 1
+  %0 = bitcast %class._ZTS3Foo.Foo* %Foo to i8*
+  call void @llvm.lifetime.start.p0i8(i64 1, i8* %0) #3
+  %1 = addrspacecast %class._ZTS3Foo.Foo* %Foo to %class._ZTS3Foo.Foo addrspace(4)*
+  call spir_func void @_ZN3FooclEv(%class._ZTS3Foo.Foo addrspace(4)* %1)
+  %2 = bitcast %class._ZTS3Foo.Foo* %Foo to i8*
+  call void @llvm.lifetime.end.p0i8(i64 1, i8* %2) #3
+  ret void
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
+
+; Function Attrs: nounwind
+define linkonce_odr spir_func void @_ZN3FooclEv(%class._ZTS3Foo.Foo addrspace(4)* %this) #2 comdat align 2 {
+entry:
+  %this.addr = alloca %class._ZTS3Foo.Foo addrspace(4)*, align 8
+  store %class._ZTS3Foo.Foo addrspace(4)* %this, %class._ZTS3Foo.Foo addrspace(4)** %this.addr, align 8, !tbaa !8
+  %this1 = load %class._ZTS3Foo.Foo addrspace(4)*, %class._ZTS3Foo.Foo addrspace(4)** %this.addr, align 8
+  ret void
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "sycl-module-id"="kernel-attrs.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { argmemonly nounwind willreturn }
+attributes #2 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.spir.version = !{!1}
+!spirv.Source = !{!2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{i32 4, i32 100000}
+!3 = !{!"clang version 10.0.0"}
+!4 = !{}
+!5 = !{i32 8}
+!6 = !{i32 1, i32 1, i32 1}
+!7 = !{i32 1}
+!8 = !{!9, !9, i64 0}
+!9 = !{!"any pointer", !10, i64 0}
+!10 = !{!"omnipotent char", !11, i64 0}
+!11 = !{!"Simple C++ TBAA"}