Sobel Filter Verilog implementation
This project involves the implementation of the Sobel algorithm using Verilog in Vivado.
You can change the image you want to load by modifying the define read_fileName "C:\\Users\\M4-249\\Desktop\\sobel_FPGA-main\\street.bmp" expression in the testbench.
This "C" extension expression indicates the path of the image.
An image with a resolution of 640x480 has been used. You can find the image size information in the module named "sobel_data_modulate.v".
!!!!!! Simulation is sufficient for the algorithm to work; synthesis is not required. !!!!!!