Supported MIPS instructions
Pavel I. Kryukov edited this page Mar 18, 2019
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31 revisions
Unfortunately, MIPT-MIPS supports reduced subset of MIPS instructions at the moment.
The list of unsupported instructions goes first as it may be more important. If instruction is not listed as supported or unsupported, it is not supported.
CP0 (#588)
sdbbpmtc0mfc0eret
MIPS IV Prefetches (#235)
pref
cachesyncsynci
MIPS II conditional traps (#130)
These instructions don't cause actual traps now, they print a message to the screen
teqteqitgetgeitgeiutgeutlttltitltiutltutnetnei
MIPS II likely branches (#91)
These branches operate as usual branches, but they don't provide any hint to BPU
beqlbgezlbgezallbgtzlblezlbltzlbltzallbnel
No atomicity warranty provided
ll
sc
addaddiaddiuadduandandibeqbgezbgezalbgtzblezbltzbltzalbnebreakcloclzdadddaddidaddiudaddudclodclzddivddivudivdivudmultdmultudslldsllvdsll32dsradsra32dsravdsrldsrl32dsrlvdsubdsubujjaljalrjrlblbuldldlldrlldlhlhuluilwlwllwrlwumaddmaddumfhimflomovnmovzmsubmsubumthimtlomulmultmultunorororisbscdsdshsdlsdrsllsllvsltsltisltiusltusrasravsrlsrlvsubsubuswswlswrsyscallxorxori
MIPT-V / MIPT-MIPS — Cycle-accurate pre-silicon simulation.