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Timing issue?
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@jotego
jotego committed Apr 27, 2019
1 parent 71960f6 commit 231b737
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Showing 14 changed files with 356 additions and 92 deletions.
4 changes: 3 additions & 1 deletion Arcade-1943.qsf
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Expand Up @@ -29,7 +29,7 @@ set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
Expand Down Expand Up @@ -376,4 +376,6 @@ set_location_assignment FRACTIONALPLL_X89_Y1_N0 -to "emu:emu|pll:pll|pll_0002:pl
set_location_assignment FRACTIONALPLL_X89_Y1_N0 -to "emu:emu|pll:pll|pll_0002:pll_inst|altera_pll:altera_pll_i|general[1].gpll"
set_location_assignment FRACTIONALPLL_X89_Y1_N0 -to "emu:emu|pll:pll|pll_0002:pll_inst|altera_pll:altera_pll_i|general[2].gpll"

set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_MACRO "AVATARS=<None>"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
128 changes: 128 additions & 0 deletions avatar_pal.hex
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Expand Up @@ -126,3 +126,131 @@ EC1
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4 changes: 3 additions & 1 deletion jt_gng/1943/hdl/jt1943.qip
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Expand Up @@ -11,11 +11,13 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt1943_
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt1943_obj.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt1943_objdraw.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt1943_security.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_prom.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_cen.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_timer.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_prom.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_ram.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_objdma.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_objbuf.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_objpxl.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_dual_ram.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jtgng_true_dual_ram.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../modules/jt12/hdl/jt12_rst.v ]
31 changes: 22 additions & 9 deletions jt_gng/1943/hdl/jt1943_char.v
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Expand Up @@ -35,7 +35,7 @@ module jt1943_char(
output [ 7:0] dout,
input rd_n,
input wr_n,
output wait_n,
output cpu_wait,
output [ 3:0] char_pxl,
// Pause screen
input pause,
Expand All @@ -57,7 +57,8 @@ reg [1:0] char_col;
wire [8:0] Hfix_prev = H+HOFFSET;
wire [8:0] Hfix = !Hfix_prev[8] && H[8] ? Hfix_prev|9'h80 : Hfix_prev; // Corrects pixel output offset

wire sel_scan = ~Hfix[2];
reg sel_scan;
// wire sel_scan = ~Hfix[2];
wire [9:0] scan = { {10{flip}}^{V128[7:3],Hfix[7:3]}};
wire [9:0] addr = sel_scan ? scan : AB[9:0];
wire we = !sel_scan && char_cs && !wr_n;
Expand Down Expand Up @@ -87,6 +88,7 @@ jtgng_ram #(.aw(10),.simfile("zeros1k.bin")) u_ram_high(

// Pause screen message
wire cen_pause = cen6 & pause;

jtgng_ram #(.aw(10),.synfile("msg.hex"),.simfile("msg.bin")) u_ram_msg(
.clk ( clk ),
.cen ( cen_pause ),
Expand All @@ -96,6 +98,7 @@ jtgng_ram #(.aw(10),.synfile("msg.hex"),.simfile("msg.bin")) u_ram_msg(
.q ( mem_msg )
);

`ifdef AVATARS
wire [7:0] av_scan = { avatar_idx, scan[9:5] };

jtgng_ram #(.aw(8),.synfile("msg_av.hex")) u_ram_msg_av(
Expand All @@ -107,22 +110,32 @@ jtgng_ram #(.aw(8),.synfile("msg_av.hex")) u_ram_msg_av(
.q ( mem_msg_av )
);

always @(*) begin
av_col = scan[4:0] == 5'd9;
msg_sel = av_col ? mem_msg_av : mem_msg;
end
`else
always @(*) msg_sel = mem_msg;
`endif

reg av_col;
reg [7:0] msg_sel;

always @(*) begin
av_col = scan[4:0] == 5'd9;
msg_sel = av_col ? mem_msg_av : mem_msg;
dout_low = pause ? msg_sel : mem_low;
dout_high = pause ? 8'h2 : mem_high;
end

// The original board gates the CPU clock instead of using wait_n
reg latch_wait_n = 1'b1;
assign wait_n = !( char_cs && sel_scan ) && latch_wait_n; // hold CPU

always @(posedge clk) if(cpu_cen)
latch_wait_n <= !( char_cs && sel_scan );
// assign wait_n = !( char_cs && sel_scan ); // hold CPU
assign cpu_wait = sel_scan;
always @(posedge clk)
if(cen6) begin
if( Hfix[2:0] == 3'b111 )
sel_scan <= 1'b1;
if( Hfix[2:0] == 3'b011 )
sel_scan <= 1'b0;
end

// Draw pixel on screen
reg [15:0] chd;
Expand Down
16 changes: 11 additions & 5 deletions jt_gng/1943/hdl/jt1943_game.v
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Expand Up @@ -88,7 +88,7 @@ wire HINIT;
wire [12:0] cpu_AB;
wire char_cs;
wire flip;
wire [7:0] cpu_dout;
wire [ 7:0] cpu_dout;
wire [ 7:0] chram_dout;
wire rd;
wire rom_ready;
Expand Down Expand Up @@ -144,7 +144,7 @@ wire [ 7:0] main_dout;
wire [15:0] char_dout, obj_dout, map1_dout, map2_dout, scr1_dout, scr2_dout;

wire snd_latch_cs;
wire char_wait_n;
wire char_wait;

wire [12:0] prom_we;

Expand Down Expand Up @@ -185,6 +185,7 @@ wire CHON, OBJON, SC2ON, SC1ON;
wire cpu_cen, main_cs;
wire OKOUT, blcnten, bus_req, bus_ack;
wire [12:0] obj_AB;
wire main_ok;

//wire video_flip = dip_flip ^ flip; // Original 1943 did not have this DIP bit.

Expand All @@ -194,7 +195,8 @@ jt1943_main u_main(
.clk ( clk ),
.cen6 ( cen6 ),
.cen3 ( cen3 ),
.char_wait_n( char_wait_n ),
.char_wait( char_wait ),
.rom_ok ( main_ok ),
// sound
.sres_b ( sres_b ),
.snd_latch_cs ( snd_latch_cs ),
Expand Down Expand Up @@ -227,7 +229,7 @@ jt1943_main u_main(
.bus_req ( bus_req ),
.bus_ack ( bus_ack ),
// ROM
.main_cs ( main_cs ),
.rom_cs ( main_cs ),
.rom_addr ( main_addr ),
.rom_data ( main_dout ),
// Cabinet input
Expand Down Expand Up @@ -276,6 +278,7 @@ jt1943_sound u_sound (
.prog_addr ( prog_addr[14:0]),
.prom_4k_we ( prom_4k_we ),
.prom_din ( prog_data ),
// Sound
.snd ( snd )
);
`else
Expand Down Expand Up @@ -306,7 +309,7 @@ jt1943_video u_video(
.chram_dout ( chram_dout ),
.char_addr ( char_addr ), // CHAR ROM
.char_data ( char_dout ),
.char_wait_n( char_wait_n ),
.char_wait ( char_wait ),
.CHON ( CHON ),
// SCROLL - ROM
.scr1posh_cs( scr1posh_cs ),
Expand Down Expand Up @@ -371,7 +374,10 @@ jt1943_rom2 u_rom (
.LHBL ( LHBL ),
.LVBL ( LVBL ),
.sdram_re ( sdram_re ),

.main_cs ( main_cs ),
.main_ok ( main_ok ),

.char_addr ( char_addr ), // 32 kB
.main_addr ( main_addr ), // 160 kB, addressed as 8-bit words
.obj_addr ( obj_addr ), // 256 kB
Expand Down

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