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The difference in seq/random write workloads mainly stems from FTL mgmt/GC efficiency, from this perspective, yes, FEMU can simulate the above scenario. It's better for you to compose some workloads and observe the performance difference directly on FEMU.
If you're talking about low-level NAND Flash commands optimized for handling adjacent seq/rand accesses, no, those are not modeled by in FEMU's NAND timing model.
As the title, are the differences between sequential and random performance considered in the delay model?
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