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Request for a more detailed guide on how to implement generated hardware on FPGA #34
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An guide or a picture for how to connect the IP block with an Zynq ultrascale MPSOC block for verifacation of the torchvision_onnx_vgg11 pynq example would be much appreciated for example. |
Sorry for the delayed response. |
Dear @shtaxxx, Your response is very much appreciated, however even with this guide the output buffer still returns 0(see picture). As far as I am aware I followed the guide presented on the website, is it possible Shtaxxx that you can verify my output, so I know that my ultra 96 v2 is not broken? I wonder if this problem is just on my end or also on yours. Thank you in advance, |
@ChristiaanBoe |
Hello everyone,
As someone who has almost no background in digital electronics a more detailed guide (or perhaps a walkthrough using one of the example codes) on how to implement the generated NNgen hardware on an FPGA and how to run the synthesized hardware (for example the IP-XACT) onto an FPGA would be appreciated.
My main Problems consist of how to implement the .npy file and write it on the off-chip memory.
And how this off-chip-memory is connected to the generated HDL.
From my limited digital electronics knowledge, the generated hardware has AXI4 or an AXI memory mapped interface so does this mean that binary code from the NPY file simply gets written from the off-chip memory to all of the addresses corresponding to different layers when that layer is in use?
A more detailed example of how the input is written towards this AXI interface would also be good for validation.
A more detailed guide with an example in the Read me or in the comments would be highly appreciated.
Thank you in advance and kind regards
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