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A VHDL-designed digital circuit simulation project to identify and record the top 10 numbers from a serial data stream using Quartus Prime 20.1.

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NajimAlfutini/Parallel-in-Serial-Out-Shift-Register

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Parallel-in-Serial-Out Shift Register

Objective

The goal of this project is to design and implement a digital circuit capable of identifying the top 10 highest numbers from a serial input stream. The results are then stored in a designated output file for further analysis or display.

Project Overview

Utilizing the robust VHDL language and leveraging the power of Field Programmable Gate Arrays (FPGAs), this project introduces a sophisticated digital circuit. The core of the design is an array of Processing Elements (PEs) coupled with a parallel-in serial-out shift register, which together processes the incoming stream of numbers to extract the highest values efficiently.

Implementation Details

  • Language Used: VHDL
  • Software Used: Quartus Prime 20.1

This system is particularly useful in applications where real-time data processing is crucial, such as in sensor data analysis or financial market monitoring. The use of FPGAs allows for high-speed data processing and the flexibility to reconfigure the circuitry as needed for different applications or updates to the algorithm.

This figure shows the design of the circuit

Parallel in Serial-out Shift Register diagram

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A VHDL-designed digital circuit simulation project to identify and record the top 10 numbers from a serial data stream using Quartus Prime 20.1.

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