NeilNie / BasicSequentialLogic_Lab3 Public

Notifications You must be signed in to change notification settings
Fork 0
Star 0

The purpose is to investigate latches, flip-flops, and registers. DA CS 603

0 stars 0 forks Branches Tags Activity

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
Part1		Part1
Part2		Part2
Part3		Part3
Part4		Part4
Part5		Part5
DE2_115_pin_assignments.csv		DE2_115_pin_assignments.csv
LICENSE		LICENSE
README.md		README.md

Repository files navigation

Basic Sequential Logic Lab in Verilog

The purpose of this exercise is to investigate latches, flip-flops, and registers.

About

The purpose is to investigate latches, flip-flops, and registers. DA CS 603

vhdl verilog verilog-hdl

Report repository

Releases

No releases published

Packages

No packages published

Languages