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ppc64.risu
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ppc64.risu
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###############################################################################
# Copyright (c) IBM Corp, 2016
# All rights reserved. This program and the accompanying materials
# are made available under the terms of the Eclipse Public License v1.0
# which accompanies this distribution, and is available at
# http://www.eclipse.org/legal/epl-v10.html
#
# Contributors:
# Jose Ricardo Ziviani - initial implementation
# based on aarch64.risu by Claudio Fontana
# based on arm.risu by Peter Maydell
###############################################################################
# Input file for risugen defining PowerPC64 instructions
.mode ppc64
# format:XO book:I page:70 v:P1 SR add Add
ADD PPC64LE 011111 rt:5 ra:5 rb:5 01000010100 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:70 v:P1 SR add Add
ADDd PPC64LE 011111 rt:5 ra:5 rb:5 01000010101 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:70 v:P1 SR add Add
ADDo PPC64LE 011111 rt:5 ra:5 rb:5 11000010100 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:70 v:P1 SR add Add
ADDdo PPC64LE 011111 rt:5 ra:5 rb:5 11000010101 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:71 v:P1 SR addc Add Carrying
ADDC PPC64LE 011111 rt:5 ra:5 rb:5 00000010100 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:71 v:P1 SR addc. Add Carrying
ADDCd PPC64LE 011111 rt:5 ra:5 rb:5 00000010101 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:71 v:P1 SR addco Add Carrying
ADDCo PPC64LE 011111 rt:5 ra:5 rb:5 10000010100 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:71 v:P1 SR addco. Add Carrying
ADDCdo PPC64LE 011111 rt:5 ra:5 rb:5 10000010101 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:72 v:P1 SR adde Add Extended
ADDE PPC64LE 011111 rt:5 ra:5 rb:5 00100010100 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:71 v:P1 SR adde. Add Extended
ADDEd PPC64LE 011111 rt:5 ra:5 rb:5 00100010101 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:71 v:P1 SR addeo Add Extended
ADDEo PPC64LE 011111 rt:5 ra:5 rb:5 10100010100 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:72 v:P1 SR addeo. Add Extended
ADDEdo PPC64LE 011111 rt:5 ra:5 rb:5 10100010101 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:110 v:2.06 addg6s Add & Generate Sixes
ADDG6S PPC64LE 111111 rt:5 ra:5 rb:5 00010010100 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:D book:I page:68 v:P1 addi Add Immediate
ADDI PPC64LE 001110 rt:5 ra:5 imm:16 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:D book:I page:70 v:P1 SR addic Add Immediate Carrying
ADDIC PPC64LE 001100 rt:5 ra:5 imm:16 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:D book:I page:70 v:P1 SR addic. Add Immediate Carrying & record
ADDICd PPC64LE 001101 rt:5 ra:5 imm:16 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:D book:I page:68 v:P1 addis Add Immediate Shifted
ADDIS PPC64LE 001111 rt:5 ra:5 imm:16 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:XO book:I page:72 v:P1 SR addme Add to Minus One Extended
ADDME PPC64LE 011111 rt:5 ra:5 0000000111010100 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:XO book:I page:72 v:P1 SR addme. Add to Minus One Extended
ADDMEd PPC64LE 011111 rt:5 ra:5 0000000111010101 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:XO book:I page:72 v:P1 SR addmeo Add to Minus One Extended
ADDMEo PPC64LE 011111 rt:5 ra:5 0000010111010100 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:XO book:I page:72 v:P1 SR addmeo. Add to Minus One Extended
ADDMEdo PPC64LE 011111 rt:5 ra:5 0000010111010101 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:DX book:I page:69 v3.0 addpcis Add PC Immediate Shifted
ADDPCIS PPC64LE 010011 rt:5 db:5 da:10 00010 dc:1 \
!constraints { $rt != 1 && $rt != 13; }
# format:XO book:I page:73 v:P1 SR addze Add to Zero Extended
ADDZE PPC64LE 011111 rt:5 ra:5 0000000110010100 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:XO book:I page:73 v:P1 SR addze. Add to Zero Extended
ADDZEd PPC64LE 011111 rt:5 ra:5 0000000110010101 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:XO book:I page:73 v:P1 SR addzeo Add to Zero Extended
ADDZEo PPC64LE 011111 rt:5 ra:5 0000010110010100 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:XO book:I page:73 v:P1 SR addze.o Add to Zero Extended
ADDZEdo PPC64LE 011111 rt:5 ra:5 0000010110010100 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; }
# format:X book:I page:93 v:P1 SR and AND
AND PP64LE 011111 rs:5 ra:5 rb:5 00000111000 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:X book:I page:93 v:P1 SR and. AND
ANDd PPC64LE 011111 rs:5 ra:5 rb:5 00000111001 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:X book:I page:94 v:P1 SR andc AND with Complement
ANDC PPC64LE 011111 ra:5 rs:5 rb:5 00001111000 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:X book:I page:94 v:P1 SR andc. AND with Complement
ANDCd PPC64LE 011111 ra:5 rs:5 rb:5 00001111001 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:D book:I page:91 v:P1 SR andi. AND Immediate & record
ANDId PPC64LE 011100 rs:5 ra:5 imm:16 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13 && $imm >= 0; }
# format:D book:I page:91 v:P1 SR andis. AND Immediate Shifted & record
ANDISd PPC64LE 011101 rs:5 ra:5 imm:16 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13 && $imm >= 0; }
# format:VX book:I page:351 v2.07 bcdadd. Decimal Add Modulo & record
BCDADDd PPC64LE 000100 vrt:5 vra:5 vrb:5 1 ps:1 000000001
# format:VX book:I page:352 v3.0 bcdcfn. Decimal Convert From National & record
BCDCFNd PPC64LE 000100 vrt:5 00111 vrb:5 1 ps:1 110000001
# format:VX book:I page:356 v3.0 bcdcfsq. Decimal Convert From Signed Qword & record
BCDCFSQd PPC64LE 000100 vrt:5 00010 vrb:5 1 ps:1 110000001
# format:VX book:I page:353 v3.0 bcdcfz. Decimal Convert From Zoned & record
BCDCFZd PPC64LE 000100 vrt:5 00110 vrb:5 1 ps:1 110000001
# format:VX book:I page:358 v3.0 bcdcpsgn. Decimal CopySign & record
BCDCPSGNd PPC64LE 000100 vrt:5 vra:5 vrb:5 01101000001
# format:VX book:I page:354 v3.0 bcdctn. Decimal Convert To National & record
BCDCTNd PPC64LE 000100 vrt:5 00101 vrb:5 10110000001
# format:VX book:I page:356 v3.0 bcdctsq. Decimal Convert To Signed Qword & record
BCDCTSQd PPC64LE 000100 vrt:5 00000 vrb:5 10110000001
# format:VX book:I page:355 v3.0 bcdctz. Decimal Convert To Zoned & record
BCDCTZd PPC64LE 000100 vrt:5 00100 vrb:5 1 ps:1 110000001
# format:VX book:I page:359 v3.0 bcds. Decimal Shift & record
BCDSd PPC64LE 000100 vrt:5 vra:5 vrb:5 1 ps:1 011000001
# format:VX book:I page:358 v3.0 bcdsetsgn. Decimal Set Sign & record
BCDSETSGNd PPC64LE 000100 vrt:5 11111 vrb:5 1 ps:1 110000001
# format:VX book:I page:361 v3.0 bcdsr. Decimal Shift & Round & record
BCDSRd PPC64LE 000100 vrt:5 vra:5 vrb:5 1 ps:1 111000001
# format:VX book:I page:351 v2.07 bcdsub. Decimal Subtract Modulo & record
BCDSUBd PPC64LE 000100 vrt:5 vra:5 vrb:5 1 ps:1 001000001
# format:VX book:I page:362 v3.0 bcdtrunc. Decimal Truncate & record
BCDTRUNCd PPC64LE 000100 vrt:5 vra:5 vrb:5 1 ps:1 100000001
# format:VX book:I page:360 v3.0 bcdus. Decimal Unsigned Shift & record
BCDUSd PPC64LE 000100 vrt:5 vra:5 vrb:5 10010000001
# format:VX book:I page:363 v3.0 bcdutrunc. Decimal Unsigned Truncate & record
BCDUTRUNCd PPC64LE 000100 vrt:5 vra:5 vrb:5 10101000001
# format:X book:I page:99 v2.06 bpermd Bit Permute Dword
BPERMD PPC64LE 011111 rs:5 ra:5 rb:5 00111111000 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:X book:I page:110 v2.06 cbcdtd Convert Binary Coded Decimal To Declets
CBCDTD PPC64LE 011111 rs:5 ra:5 0000001001110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:110 v2.06 cdtbcd Convert Declets To Binary Coded Decimal
CDTBCD PPC64LE 011111 rs:5 ra:5 0000001000110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:44 v2.07 clrbhrb Clear BHRB
CLRBHRB PPC64LE 011111 00000000000000001101011100
# format:X book:I page:85 v:P1 cmp Compare
CMP PPC64LE 011111 bf:3 0 l:1 ra:5 rb:5 00000000000 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; }
# format:X book:I page:96 v2.05 cmpb Compare Bytes
CMPB PPC64LE 011111 rs:5 ra:5 rb:5 01111111000 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:X book:I page:88 v3.0 cmpeqb Compare Equal Byte
CMPEQB PPC64LE 011111 bf:3 00 ra:5 rb:5 00111000000 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; }
# format:D book:I page:85 v:P1 cmpi Compare Immediate
CMPI PPC64LE 001011 bf:3 0 l:1 ra:5 imm:16 \
!constraints { $ra != 1 && $ra != 13; }
# format:X book:I page:86 v:P1 cmpl Compare Logical
CMPL PPC64LE 011111 bf:3 0 l:1 ra:5 rb:5 00001000000 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; }
# format:D book:I page:86 v:P1 cmpli Compare Logical Immediate
CMPLI PPC64LE 001010 bf:3 0 l:1 ra:5 imm:16 \
!constraints { $ra != 1 && $ra != 13 && $imm >= 0; }
# format:X book:I page:87 v3.0 cmprb Compare Ranged Byte
CMPRB PPC64LE 011111 bf:3 0 l:1 ra:5 rb:5 00110000000 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; }
# format:X book:I page:98 PPC SR cntlzd Count Leading Zeros Dword
CNTLZD PPC64LE 011111 rs:5 ra:5 0000000001110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:98 PPC SR cntlzd. Count Leading Zeros Dword
CNTLZDd PPC64LE 011111 rs:5 ra:5 0000000001110101 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:95 v:P1 SR cntlzw Count Leading Zeros Word
CNTLZW PPC64LE 011111 rs:5 ra:5 0000000000110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:95 v:P1 SR cntlzw. Count Leading Zeros Word
CNTLZWd PPC64LE 011111 rs:5 ra:5 0000000000110101 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:98 v3.0 cnttzd Count Trailing Zeros Dword
CNTTZD PPC64LE 011111 rs:5 ra:5 0000010001110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:98 v3.0 cnttzd. Count Trailing Zeros Dword
CNTTZDd PPC64LE 011111 rs:5 ra:5 0000010001110101 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:95 v3.0 cnttzw Count Trailing Zeros Word
CNTTZW PPC64LE 011111 rs:5 ra:5 0000010000110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:95 v3.0 cnttzw. Count Trailing Zeros Word
CNTTZWd PPC64LE 011111 rs:5 ra:5 0000010000110101 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:XL book:I page:41 v:P1 crand CR AND
CRAND PPC64LE 010011 bt:5 ba:5 bb:5 01000000010
# format:XL book:I page:42 v:P1 crandc CR AND with Complement
CRANDC PPC64LE 010011 bt:5 ba:5 bb:5 00100000010
# format:XL book:I page:42 v:P1 creqv CR Equivalent
CREQV PPC64LE 010011 bt:5 ba:5 bb:5 01001000010
# format:XL book:I page:41 v:P1 crnand CR NAND
CRNAND PPC64LE 010011 bt:5 ba:5 bb:5 00111000010
# format:XL book:I page:42 v:P1 crnor CR NOR
CRNOR PPC64LE 010011 bt:5 ba:5 bb:5 00001000010
# format:XL book:I page:41 v:P1 cror CR OR
CROR PPC64LE 010011 bt:5 ba:5 bb:5 01110000010
# format:XL book:I page:42 v:P1 crorc CR OR with Complement
CRORC PPC64LE 010011 bt:5 ba:5 bb:5 01101000010
# format:XL book:I page:41 v:P1 crxor CR XOR
CRXOR PPC64LE 010011 bt:5 ba:5 bb:5 00110000010
# format:X book:I page:195 v2.05 dadd DFP Add
DADD PPC64LE 111011 frt:5 fra:5 frb:5 00000000100
# format:X book:I page:195 v2.05 dadd. DFP Add
DADDd PPC64LE 111011 frt:5 fra:5 frb:5 00000000101
# format:X book:I page:195 v2.05 daddq DFP Add Quad
DADDQ PPC64LE 111111 frtp:5 frap:5 frbp:5 00000000100
# format:X book:I page:195 v2.05 daddq. DFP Add Quad
DADDQd PPC64LE 111111 frtp:5 frap:5 frbp:5 00000000101
# format:X book:I page:79 v3.0 darn Deliver A Random Number
DARN PPC64LE 011111 rt:5 000 l:2 0000010111100110 \
!constraints { $rt != 1 && $rt != 13 && $l != 3; }
# format:X book:I page:217 v2.06 dcffix DFP Convert From Fixed
DCFFIX PPC64LE 111011 frt:5 00000 frb:5 11001000100
# format:X book:I page:217 v2.06 dcffix. DFP Convert From Fixed
DCFFIXd PPC64LE 111011 frt:5 00000 frb:5 11001000101
# format:X book:I page:217 v2.05 dcffixq DFP Convert From Fixed Quad
DCFFIXQ PPC64LE 111111 frt:5 00000 frbp:5 11001000100
# format:X book:I page:217 v2.05 dcffixq. DFP Convert From Fixed Quad
DCFFIXQd PPC64LE 111111 frt:5 00000 frbp:5 11001000101
# format:X book:I page:201 v2.05 dcmpo DFP Compare Ordered
DCMPO PPC64LE 111011 bf:3 00 fra:5 frb:5 00100000100
# format:X book:I page:201 v2.05 dcmpoq DFP Compare Ordered Quad
DCMPOQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 00100000100
# format:X book:I page:200 v2.05 dcmpu DFP Compare Unordered
DCMPU PPC64LE 111011 bf:3 00 fra:5 frb:5 10100000100
# format:X book:I page:200 v2.05 dcmpuq DFP Compare Unordered Quad
DCMPUQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 10100000100
# format:X book:I page:215 v2.05 dctdp DFP Convert To DFP Long
DCTDP PPC64LE 111011 frt:5 00000 frb:5 01000000100
# format:X book:I page:215 v2.05 dctdp. DFP Convert To DFP Long
DCTDPd PPC64LE 111011 frt:5 00000 frb:5 01000000101
# format:X book:I page:217 v2.05 dctfix DFP Convert To Fixed
DCTFIX PPC64LE 111011 frt:5 00000 frb:5 01001000100
# format:X book:I page:217 v2.05 dctfix. DFP Convert To Fixed
DCTFIXd PPC64LE 111011 frt:5 00000 frb:5 01001000101
# format:X book:I page:217 v2.05 dctfixq DFP Convert To Fixed Quad
DCTFIXQ PPC64LE 111111 frt:5 00000 frbq:5 01001000100
# format:X book:I page:217 v2.05 dctfixq. DFP Convert To Fixed Quad
DCTFIXQd PPC64LE 111111 frt:5 00000 frbq:5 01001000101
# format:X book:I page:215 v2.05 dctqpq DFP Convert To DFP Extended
DCTQPQ PPC64LE 111111 frtp:5 00000 frb:5 01000000100
# format:X book:I page:215 v2.05 dctqpq. DFP Convert To DFP Extended
DCTQPQd PPC64LE 111111 frtp:5 00000 frb:5 01000000101
# format:X book:I page:219 v2.05 ddedpd DFP Decode DPD To BCD
DDEDPD PPC64LE 111011 frt:5 sp:2 000 frb:5 01010000100
# format:X book:I page:219 v2.05 ddedpd. DFP Decode DPD To BCD
DDEDPDd PPC64LE 111011 frt:5 sp:2 000 frb:5 01010000101
# format:X book:I page:219 v2.05 ddedpdq DFP Decode DPD To BCD Quad
DDEDPDQ PPC64LE 111111 frtp:5 sp:2 000 frbp:5 01010000100
# format:X book:I page:219 v2.05 ddedpdq. DFP Decode DPD To BCD Quad
DDEDPDQd PPC64LE 111111 frtp:5 sp:2 000 frbp:5 01010000101
# format:X book:I page:198 v2.05 ddiv DFP Divide
DDIV PPC64LE 111011 frt:5 fra:5 frb:5 10001000100
# format:X book:I page:198 v2.05 ddiv. DFP Divide
DDIVd PPC64LE 111011 frt:5 fra:5 frb:5 10001000101
# format:X book:I page:198 v2.05 ddivq DFP Divide Quad
DDIVQ PPC64LE 111111 frtp:5 frap:5 frbp:5 10001000100
# format:X book:I page:198 v2.05 ddivq. DFP Divide Quad
DDIVQd PPC64LE 111111 frtp:5 frap:5 frbp:5 10001000101
# format:X book:I page:219 v2.05 denbcd DFP Encode BCD To DPD
DENBCD PPC64LE 111011 frt:5 s:1 0000 frb:5 11010000100
# format:X book:I page:219 v2.05 denbcd. DFP Encode BCD To DPD
DENBCDd PPC64LE 111011 frt:5 s:1 0000 frb:5 11010000101
# format:X book:I page:219 v2.05 denbcdq DFP Encode BCD To DPD Quad
DENBCDQ PPC64LE 111111 frtp:5 s:1 0000 frbp:5 11010000100
# format:X book:I page:219 v2.05 denbcdq. DFP Encode BCD To DPD Quad
DENBCDQd PPC64LE 111111 frtp:5 s:1 0000 frbp:5 11010000101
# format:X book:I page:220 v2.05 diex DFP Insert Exponent
DIEX PPC64LE 111011 frt:5 fra:5 frb:5 11011000100
# format:X book:I page:220 v2.05 diex. DFP Insert Exponent
DIEXd PPC64LE 111011 frt:5 fra:5 frb:5 11011000101
# format:X book:I page:220 v2.05 diexq DFP Insert Exponent Quad
DIEXQ PPC64LE 111111 frtp:5 fra:5 frbp:5 11011000100
# format:X book:I page:220 v2.05 diexq. DFP Insert Exponent Quad
DIEXQd PPC64LE 111111 frtp:5 fra:5 frbp:5 11011000101
# format:XO book:I page:82 PPC SR divd Divide Dword
DIVD PPC64LE 011111 rt:5 ra:5 rb:5 01111010010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:82 PPC SR divd. Divide Dword
DIVDd PPC64LE 011111 rt:5 ra:5 rb:5 01111010011 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:82 PPC SR divdo Divide Dword
DIVDo PPC64LE 011111 rt:5 ra:5 rb:5 11111010010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:82 PPC SR divdo. Divide Dword
DIVDod PPC64LE 011111 rt:5 ra:5 rb:5 11111010011 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:83 v2.06 SR divde Divide Dword Extended
DIVDE PPC64LE 011111 rt:5 ra:5 rb:5 01101010010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:83 v2.06 SR divde. Divide Dword Extended
DIVDEd PPC64LE 011111 rt:5 ra:5 rb:5 01101010011 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:83 v2.06 SR divdeo Divide Dword Extended
DIVDEo PPC64LE 011111 rt:5 ra:5 rb:5 11101010010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:83 v2.06 SR divdeo. Divide Dword Extended
DIVDEod PPC64LE 011111 rt:5 ra:5 rb:5 11101010011 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:83 v2.06 SR divdeu Divide Dword Extended Unsigned
DIVDEU PPC64LE 011111 rt:5 ra:5 rb:5 01100010010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:83 v2.06 SR divdeu. Divide Dword Extended Unsigned
DIVDEUd PPC64LE 011111 rt:5 ra:5 rb:5 01100010011 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:83 v2.06 SR divdeuo Divide Dword Extended Unsigned
DIVDEUo PPC64LE 011111 rt:5 ra:5 rb:5 11100010010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:83 v2.06 SR divdeuo. Divide Dword Extended Unsigned
DIVDEUod PPC64LE 011111 rt:5 ra:5 rb:5 11100010011 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:82 PPC SR divdu Divide Dword Unsigned
DIVDU PPC64LE 011111 rt:5 ra:5 rb:5 01110010010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:82 PPC SR divdu. Divide Dword Unsigned
DIVDUd PPC64LE 011111 rt:5 ra:5 rb:5 01110010011 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:82 PPC SR divduo Divide Dword Unsigned
DIVDUo PPC64LE 011111 rt:5 ra:5 rb:5 11110010010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:82 PPC SR divduo. Divide Dword Unsigned
DIVDUod PPC64LE 011111 rt:5 ra:5 rb:5 11110010011 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:75 PPC SR divw Divide Word
DIVW PPC64LE 011111 rt:5 ra:5 rb:5 01111010110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:75 PPC SR divw. Divide Word
DIVWd PPC64LE 011111 rt:5 ra:5 rb:5 01111010111 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:75 PPC SR divwo Divide Word
DIVWo PPC64LE 011111 rt:5 ra:5 rb:5 11111010110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:75 PPC SR divwo. Divide Word
DIVWod PPC64LE 011111 rt:5 ra:5 rb:5 11111010111 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:77 v2.06 SR divwe Divide Word Extended
DIVWE PPC64LE 011111 rt:5 ra:5 rb:5 01101010110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:77 v2.06 SR divwe. Divide Word Extended
DIVWEd PPC64LE 011111 rt:5 ra:5 rb:5 01101010111 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:77 v2.06 SR divweo Divide Word Extended
DIVWEo PPC64LE 011111 rt:5 ra:5 rb:5 11101010110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:77 v2.06 SR divweo. Divide Word Extended
DIVWEod PPC64LE 011111 rt:5 ra:5 rb:5 11101010111 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:77 v2.06 SR divweu Divide Word Extended Unsigned
DIVWEU PPC64LE 011111 rt:5 ra:5 rb:5 01100010110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:77 v2.06 SR divweu. Divide Word Extended Unsigned
DIVWEUd PPC64LE 011111 rt:5 ra:5 rb:5 01100010111 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:77 v2.06 SR divweuo Divide Word Extended Unsigned
DIVWEUo PPC64LE 011111 rt:5 ra:5 rb:5 11100010110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:77 v2.06 SR divweuo. Divide Word Extended Unsigned
DIVWEUod PPC64LE 011111 rt:5 ra:5 rb:5 11100010111 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:75 PPC SR divwu Divide Word Unsigned
DIVWU PPC64LE 011111 rt:5 ra:5 rb:5 01110010110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:75 PPC SR divwu. Divide Word Unsigned
DIVWUd PPC64LE 011111 rt:5 ra:5 rb:5 01110010111 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:75 PPC SR divwuo Divide Word Unsigned
DIVWUo PPC64LE 011111 rt:5 ra:5 rb:5 11110010110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:XO book:I page:75 PPC SR divwuo. Divide Word Unsigned
DIVWUod PPC64LE 011111 rt:5 ra:5 rb:5 11110010111 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:X book:I page:197 v2.05 dmul DFP Multiply
DMUL PPC64LE 111011 frt:5 fra:5 frb:5 00001000100
# format:X book:I page:197 v2.05 dmul. DFP Multiply
DMULd PPC64LE 111011 frt:5 fra:5 frb:5 00001000101
# format:X book:I page:197 v2.05 dmulq DFP Multiply Quad
DMULQ PPC64LE 111111 frt:5 fra:5 frb:5 00001000100
# format:X book:I page:197 v2.05 dmulq. DFP Multiply Quad
DMULQd PPC64LE 111111 frt:5 fra:5 frb:5 00001000101
# format:Z23 book:I page:206 v2.05 dqua DFP Quantize
DQUA PPC64LE 111011 frt:5 fra:5 frb:5 rmc:2 000000110
# format:Z23 book:I page:206 v2.05 dqua. DFP Quantize
DQUAd PPC64LE 111011 frt:5 fra:5 frb:5 rmc:2 000000111
# format:Z23 book:I page:205 v2.05 dquai DFP Quantize Immediate
DQUAI PPC64LE 111011 frt:5 te:5 frb:5 rmc:2 010000110
# format:Z23 book:I page:205 v2.05 dquai. DFP Quantize Immediate
DQUAId PPC64LE 111011 frt:5 te:5 frb:5 rmc:2 010000111
# format:Z23 book:I page:205 v2.05 dquaiq DFP Quantize Immediate Quad
DQUAIQ PPC64LE 111111 frtp:5 te:5 frbp:5 rmc:2 010000110
# format:Z23 book:I page:205 v2.05 dquaiq. DFP Quantize Immediate Quad
DQUAIQd PPC64LE 111111 frtp:5 te:5 frbp:5 rmc:2 010000111
# format:Z23 book:I page:206 v2.05 dquaq DFP Quantize Quad
DQUAQ PPC64LE 111111 frtp:5 frap:5 frbp:5 rmc:2 000000110
# format:Z23 book:I page:206 v2.05 dquaq. DFP Quantize Quad
DQUAQd PPC64LE 111111 frtp:5 frap:5 frbp:5 rmc:2 000000111
# format:X book:I page:216 v2.05 drdpq DFP Round To DFP Long
DRDPQ PPC64LE 111111 frtp:5 00000 frbp:5 11000000100
# format:X book:I page:216 v2.05 drdpq. DFP Round To DFP Long
DRDPQd PPC64LE 111111 frtp:5 00000 frbp:5 11000000101
# format:Z23 book:I page:213 v2.05 drintn DFP Round To FP Integer Without Inexact
DRINTN PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 111000110
# format:Z23 book:I page:213 v2.05 drintn. DFP Round To FP Integer Without Inexact
DRINTNd PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 111000111
# format:Z23 book:I page:213 v2.05 drintnq DFP Round To FP Integer Without Inexact Quad
DRINTNQ PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 111000110
# format:Z23 book:I page:213 v2.05 drintnq. DFP Round To FP Integer Without Inexact Quad
DRINTNQd PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 111000111
# format:Z23 book:I page:211 v2.05 drintx DFP Round To FP Integer With Inexact
DRINTX PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 011000110
# format:Z23 book:I page:211 v2.05 drintx. DFP Round To FP Integer With Inexact
DRINTXd PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 011000111
# format:Z23 book:I page:211 v2.05 drintxq DFP Round To FP Integer With Inexact Quad
DRINTXQ PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 011000110
# format:Z23 book:I page:211 v2.05 drintxq. DFP Round To FP Integer With Inexact Quad
DRINTXQd PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 011000111
# format:Z23 book:I page:208 v2.05 drrnd DFP Reround
DRRND PPC64LE 111011 frt:5 fra:5 frb:5 rmc:2 001000110
# format:Z23 book:I page:208 v2.05 drrnd. DFP Reround
DRRNDd PPC64LE 111011 frt:5 fra:5 frb:5 rmc:2 001000111
# format:Z23 book:I page:208 v2.05 drrndq DFP Reround Quad
DRRNDQ PPC64LE 111111 frtp:5 fra:5 frbp:5 rmc:2 001000110
# format:Z23 book:I page:208 v2.05 drrndq. DFP Reround Quad
DRRNDQd PPC64LE 111111 frtp:5 fra:5 frbp:5 rmc:2 001000111
# format:X book:I page:216 v2.05 drsp DFP Round To DFP Short
DRSP PPC64LE 111011 frt:5 00000 frb:5 11000000100
# format:X book:I page:216 v2.05 drsp. DFP Round To DFP Short
DRSPd PPC64LE 111011 frt:5 00000 frb:5 11000000101
# format:Z22 book:I page:222 v2.05 dscli DFP Shift Significand Left Immediate
DSCLI PPC64LE 111011 frt:5 fra:5 sh:6 0010000100
# format:Z22 book:I page:222 v2.05 dscli. DFP Shift Significand Left Immediate
DSCLId PPC64LE 111011 frt:5 fra:5 sh:6 0010000101
# format:Z22 book:I page:222 v2.05 dscliq DFP Shift Significand Left Immediate Quad
DSCLIQ PPC64LE 111111 frtp:5 frap:5 sh:6 0010000100
# format:Z22 book:I page:222 v2.05 dscliq. DFP Shift Significand Left Immediate Quad
DSCLIQd PPC64LE 111111 frtp:5 frap:5 sh:6 0010000101
# format:Z22 book:I page:222 v2.05 dscri DFP Shift Significand Right Immediate
DSCRI PPC64LE 111011 frt:5 fra:5 sh:6 0011000100
# format:Z22 book:I page:222 v2.05 dscri. DFP Shift Significand Right Immediate
DSCRId PPC64LE 111011 frt:5 fra:5 sh:6 0011000101
# format:Z22 book:I page:222 v2.05 dscriq DFP Shift Significand Right Immediate Quad
DSCRIQ PPC64LE 111111 frtp:5 frap:5 sh:6 0011000100
# format:Z22 book:I page:222 v2.05 dscriq. DFP Shift Significand Right Immediate Quad
DSCRIQd PPC64LE 111111 frtp:5 frap:5 sh:6 0011000101
# format:X book:I page:195 v2.05 dsub DFP Subtract
DSUB PPC64LE 111011 frt:5 fra:5 frb:5 10000000100
# format:X book:I page:195 v2.05 dsub. DFP Subtract
DSUBd PPC64LE 111011 frt:5 fra:5 frb:5 10000000101
# format:X book:I page:195 v2.05 dsubq DFP Subtract Quad
DSUBQ PPC64LE 111111 frtp:5 frap:5 frbp:5 10000000100
# format:X book:I page:195 v2.05 dsubq. DFP Subtract Quad
DSUBQd PPC64LE 111111 frtp:5 frap:5 frbp:5 10000000101
# format:Z22 book:I page:202 v2.05 dtstdc DFP Test Data Class
DTSTDC PPC64LE 111011 bf:3 00 fra:5 dcm:6 0110000100
# format:Z22 book:I page:202 v2.05 dtstdcq DFP Test Data Class Quad
DTSTDCQ PPC64LE 111111 bf:3 00 frap:5 dcm:6 0110000100
# format:Z22 book:I page:202 v2.05 dtstdg DFP Test Data Group
DTSTDG PPC64LE 111011 bf:3 00 frap:5 dgm:6 0111000100
# format:Z22 book:I page:202 v2.05 dtstdgq DFP Test Data Group Quad
DTSTDGQ PPC64LE 111111 bf:3 00 frap:5 dgm:6 0111000100
# format:X book:I page:203 v2.05 dtstex DFP Test Exponent
DTSTEX PPC64LE 111011 bf:3 00 fra:5 frb:5 00101000100
# format:X book:I page:203 v2.05 dtstexq DFP Test Exponent Quad
DTSTEXQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 00101000100
# format:X book:I page:204 v2.05 dtstsf DFP Test Significance
DTSTSF PPC64LE 111011 bf:3 0 fra:6 frb:5 10101000100
# format:X book:I page:204 v3.0 dtstsfi DFP Test Significance Immediate
DTSTSFI PPC64LE 111011 bf:3 0 uim:6 frb:5 10101000110
# format:X book:I page:204 v3.0 dtstsfiq DFP Test Significance Immediate Quad
DTSTSFIQ PPC64LE 111111 bf:3 0 uim:6 frbp:5 10101000110
# format:X book:I page:204 v2.05 dtstsfq DFP Test Significance Quad
DTSTSFQ PPC64LE 111111 bf:3 0 fra:6 frb:5 10101000100
# format:X book:I page:220 v2.05 dxex. DFP Extract Exponent
DXEX PPC64LE 111011 frt:5 00000 frb:5 01011000100
# format:X book:I page:220 v2.05 dxex DFP Extract Exponent
DXEXd PPC64LE 111011 frt:5 00000 frb:5 01011000101
# format:X book:I page:220 v2.05 dxexq DFP Extract Exponent Quad
DEXEQ PPC64LE 111111 frt:5 00000 frbp:5 01011000100
# format:X book:I page:220 v2.05 dxexq. DFP Extract Exponent Quad
DEXEQd PPC64LE 111111 frt:5 00000 frbp:5 01011000101
# format:X book:I page:94 v:P1 SR eqv Equivalent
EQV PPC64LE 011111 rs:5 ra:5 rb:5 01000111000 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:X book:I page:94 v:P1 SR eqv. Equivalent
EQVd PPC64LE 011111 rs:5 ra:5 rb:5 01000111001 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:X book:I page:94 PPC SR extsb Extend Sign Byte
EXTSB PPC64LE 011111 rs:5 ra:5 0000011101110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:94 PPC SR extsb. Extend Sign Byte
EXTSBd PPC64LE 011111 rs:5 ra:5 0000011101110101 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:94 v:P1 SR extsh Extend Sign Hword
EXTSH PPC64LE 011111 rs:5 ra:5 0000011100110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:94 v:P1 SR extsh. Extend Sign Hword
EXTSHd PPC64LE 011111 rs:5 ra:5 0000011100110101 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:98 PPC SR extsw Extend Sign Word
EXTSW PPC64LE 011111 rs:5 ra:5 0000011110110100 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:98 PPC SR extsw. Extend Sign Word
EXTSWd PPC64LE 011111 rs:5 ra:5 0000011110110101 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:XS book:I page:109 v3.0 extswsli Extend Sign Word & Shift Left Immediate
EXTSWSLI PPC64LE 011111 rs:5 ra:5 sha:5 110111101 shb:1 0 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:XS book:I page:109 v3.0 extswsli. Extend Sign Word & Shift Left Immediate
EXTSWSLId PPC64LE 011111 rs:5 ra:5 sha:5 110111101 shb:1 1 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:X book:I page:151 v:P1 fabs Floating Absolute
FABS PPC64LE 111111 frt:5 00000 frb:5 01000010000
# format:X book:I page:151 v:P1 fabs. Floating Absolute
FABSd PPC64LE 111111 frt:5 00000 frb:5 01000010001
# format:A book:I page:153 v:P1 fadd Floating Add
FADD PPC64LE 111111 frt:5 fra:5 frb:5 00000101010
# format:A book:I page:153 v:P1 fadd. Floating Add
FADDd PPC64LE 111111 frt:5 fra:5 frb:5 00000101011
# format:A book:I page:153 PPC fadds Floating Add Single
FADDS PPC64LE 111011 frt:5 fra:5 frb:5 00000101010
# format:A book:I page:153 PPC fadds. Floating Add Single
FADDSd PPC64LE 111011 frt:5 fra:5 frb:5 00000101010
# format:X book:I page:164 PPC fcfid Floating Convert From Integer Dword
FCFID PPC64LE 111111 frt:5 00000 frb:5 11010011100
# format:X book:I page:164 PPC fcfid Floating Convert From Integer Dword
FCFIDd PPC64LE 111111 frt:5 00000 frb:5 11010011101
# format:X book:I page:165 v2.06 fcfids Floating Convert From Integer Dword Single
FCFIDS PPC64LE 111011 frt:5 00000 frb:5 11010011100
# format:X book:I page:165 v2.06 fcfids Floating Convert From Integer Dword Single
FCFIDSd PPC64LE 111011 frt:5 00000 frb:5 11010011101
# format:X book:I page:165 v2.06 fcfidu Floating Convert From Integer Dword Unsigned
FCFIDU PPC64LE 111111 frt:5 00000 frb:5 11110 011100
# format:X book:I page:165 v2.06 fcfidu Floating Convert From Integer Dword Unsigned
FCFIDUd PPC64LE 111111 frt:5 00000 frb:5 11110 011101
# format:X book:I page:166 v2.06 fcfidus Floating Convert From Integer Dword Unsigned Single
FCFIDUS PPC64LE 111011 frt:5 00000 frb:5 11110011100
# format:X book:I page:166 v2.06 fcfidus Floating Convert From Integer Dword Unsigned Single
FCFIDUSd PPC64LE 111011 frt:5 00000 frb:5 11110011101
# format:X book:I page:168 v:P1 fcmpo Floating Compare Ordered
FCMPO PPC64LE 111111 bf:3 00 fra:5 frb:5 00001000000
# format:X book:I page:168 v:P1 fcmpu Floating Compare Unordered
FCMPU PPC64LE 111111 bf:3 00 fra:5 frb:5 00000000000
# format:X book:I page:151 v2.05 fcpsgn Floating Copy Sign
FCPSGN PPC64LE 111111 frt:5 fra:5 frb:5 00000010000
# format:X book:I page:151 v2.05 fcpsgn Floating Copy Sign
FCPSGNd PPC64LE 111111 frt:5 fra:5 frb:5 00000010001
# format:X book:I page:160 PPC fctid Floating Convert To Integer Dword
FCTID PPC64LE 111111 frt:5 00000 frb:5 11001011100
# format:X book:I page:160 PPC fctid Floating Convert To Integer Dword
FCTIDd PPC64LE 111111 frt:5 00000 frb:5 11001011101
# format:X book:I page:161 v2.06 fctidu Floating Convert To Integer Dword Unsigned
FCTIDU PPC64LE 111111 frt:5 00000 frb:5 11101011100
# format:X book:I page:161 v2.06 fctidu Floating Convert To Integer Dword Unsigned
FCTIDUd PPC64LE 111111 frt:5 00000 frb:5 11101011101
# format:X book:I page:162 v2.06 fctiduz Floating Convert To Integer Dword Unsigned truncate
FCTIDUZ PPC64LE 111111 frt:5 00000 frb:5 11101011110
# format:X book:I page:162 v2.06 fctiduz Floating Convert To Integer Dword Unsigned truncate
FCTIDUZd PPC64LE 111111 frt:5 00000 frb:5 11101011111
# format:X book:I page:161 PPC fctidz Floating Convert To Integer Dword truncate
FCTIDZ PPC64LE 111111 frt:5 00000 frb:5 11001011110
# format:X book:I page:161 PPC fctidz Floating Convert To Integer Dword truncate
FCTIDZd PPC64LE 111111 frt:5 00000 frb:5 11001011111
# format:X book:I page:162 P2 fctiw Floating Convert To Integer Word
FCTIW PPC64LE 111111 frt:5 00000 frb:5 00000011100
# format:X book:I page:162 P2 fctiw Floating Convert To Integer Word
FCTIWd PPC64LE 111111 frt:5 00000 frb:5 00000011101
# format:X book:I page:163 v2.06 fctiwu Floating Convert To Integer Word Unsigned
FCTIWU PPC64LE 111111 frt:5 00000 frb:5 00100011100
# format:X book:I page:163 v2.06 fctiwu Floating Convert To Integer Word Unsigned
FCTIWUd PPC64LE 111111 frt:5 00000 frb:5 00100011101
# format:X book:I page:164 v2.06 fctiwuz Floating Convert To Integer Word Unsigned truncate
FCTIWUZ PPC64LE 111111 frt:5 00000 frb:5 00100011110
# format:X book:I page:164 v2.06 fctiwuz Floating Convert To Integer Word Unsigned truncate
FCTIWUZd PPC64LE 111111 frt:5 00000 frb:5 00100011111
# format:X book:I page:163 P2 fctiwz Floating Convert To Integer Word truncate
FCTIWZ PPC64LE 111111 frt:5 00000 frb:5 00000011110
# format:X book:I page:163 P2 fctiwz Floating Convert To Integer Word truncate
FCTIWZd PPC64LE 111111 frt:5 00000 frb:5 00000011111
# format:A book:I page:154 v:P1 fdiv Floating Divide
FDIV PPC64LE 111111 frt:5 fra:5 frb:5 00000100100
# format:A book:I page:154 v:P1 fdiv Floating Divide
FDIVd PPC64LE 111111 frt:5 fra:5 frb:5 00000100101
# format:A book:I page:154 PPC fdivs Floating Divide Single
FDIVS PPC64LE 111011 frt:5 fra:5 frb:5 00000100100
# format:A book:I page:154 PPC fdivs Floating Divide Single
FDIVSd PPC64LE 111011 frt:5 fra:5 frb:5 00000100101
# format:A book:I page:158 v:P1 fmadd Floating Multiply-Add
FMADD PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 111010
# format:A book:I page:158 v:P1 fmadd Floating Multiply-Add
FMADDd PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 111011
# format:A book:I page:158 PPC fmadds Floating Multiply-Add Single
FMADDS PPC64LE 111011 frt:5 fra:5 frb:5 frc:5 111010
# format:A book:I page:158 PPC fmadds Floating Multiply-Add Single
FMADDSd PPC64LE 111011 frt:5 fra:5 frb:5 frc:5 111011
# format:X book:I page:151 v:P1 fmr Floating Move Register
FMR PPC64LE 111111 frt:5 00000 frb:5 00010010000
# format:X book:I page:151 v:P1 fmr Floating Move Register
FMRd PPC64LE 111111 frt:5 00000 frb:5 00010010001
# format:X book:I page:151 v2.07 fmrgew Floating Merge Even Word
FMRGEW PPC64LE 111111 frt:5 fra:5 frb:5 11110001100
# format:X book:I page:152 v2.07 fmrgow Floating Merge Odd Word
FMRGOW PPC64LE 111111 frt:5 fra:5 frb:5 11010001100
# format:A book:I page:159 v:P1 fmsub Floating Multiply-Subtract
FMSUB PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 111000
# format:A book:I page:159 v:P1 fmsub Floating Multiply-Subtract
FMSUBd PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 111001
# format:A book:I page:159 PPC fmsubs Floating Multiply-Subtract Single
FMSUBS PPC64LE 111011 frt:5 fra:5 frb:5 frc:5 111000
# format:A book:I page:159 PPC fmsubs Floating Multiply-Subtract Single
FMSUBSd PPC64LE 111011 frt:5 fra:5 frb:5 frc:5 111001
# format:A book:I page:154 v:P1 fmul Floating Multiply
FMUL PPC64LE 111111 frt:5 fra:5 00000 frb:5 110010
# format:A book:I page:154 v:P1 fmul Floating Multiply
FMULd PPC64LE 111111 frt:5 fra:5 00000 frb:5 110011
# format:A book:I page:154 PPC fmuls Floating Multiply Single
FMULS PPC64LE 111011 frt:5 fra:5 00000 frb:5 110010
# format:A book:I page:154 PPC fmuls Floating Multiply Single
FMULSd PPC64LE 111011 frt:5 fra:5 00000 frb:5 110011
# format:X book:I page:151 v:P1 fnabs Floating Negative Absolute Value
FNABS PPC64LE 111111 frt:5 00000 frb:5 00100010000
# format:X book:I page:151 v:P1 fnabs Floating Negative Absolute Value
FNABSd PPC64LE 111111 frt:5 00000 frb:5 00100010001
# format:X book:I page:151 v:P1 fneg Floating Negate
FNEG PPC64LE 111111 frt:5 00000 frb:5 00001010000
# format:X book:I page:151 v:P1 fneg Floating Negate
FNEGd PPC64LE 111111 frt:5 00000 frb:5 00001010001
# format:A book:I page:159 v:P1 fnmadd Floating Negative Multiply-Add
FNMADD PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 111110
# format:A book:I page:159 v:P1 fnmadd Floating Negative Multiply-Add
FNMADDd PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 111111
# format:A book:I page:159 PPC fnmadds Floating Negative Multiply-Add Single
FNMADDS PPC64LE 111011 frt:5 fra:5 frb:5 frc:5 111110
# format:A book:I page:159 PPC fnmadds Floating Negative Multiply-Add Single
FNMADDSd PPC64LE 111011 frt:5 fra:5 frb:5 frc:5 111111
# format:A book:I page:159 v:P1 fnmsub Floating Negative Multiply-Subtract
FNMSUB PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 111100
# format:A book:I page:159 v:P1 fnmsub Floating Negative Multiply-Subtract
FNMSUBd PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 111101
# format:A book:I page:159 PPC fnmsubs Floating Negative Multiply-Subtract Single
FNMSUBS PPC64LE 111011 frt:5 fra:5 frb:5 frc:5 111100
# format:A book:I page:159 PPC fnmsubs Floating Negative Multiply-Subtract Single
FNMSUBSd PPC64LE 111011 frt:5 fra:5 frb:5 frc:5 111101
# format:A book:I page:155 v2.02 fre Floating Reciprocal Estimate
FRE PPC64LE 111111 frt:5 00000 frb:5 00000110000
# format:A book:I page:155 v2.02 fre Floating Reciprocal Estimate
FREd PPC64LE 111111 frt:5 00000 frb:5 00000110001
# format:A book:I page:155 PPC fres Floating Reciprocal Estimate Single
FRES PPC64LE 111011 frt:5 00000 frb:5 00000110000
# format:A book:I page:155 PPC fres Floating Reciprocal Estimate Single
FRESd PPC64LE 111011 frt:5 00000 frb:5 00000110001
# format:X book:I page:167 v2.02 frim Floating Round To Integer Minus
FRIM PPC64LE 111111 frt:5 00000 frb:5 01111 010000
# format:X book:I page:167 v2.02 frim Floating Round To Integer Minus
FRIMd PPC64LE 111111 frt:5 00000 frb:5 01111 010001
# format:X book:I page:167 v2.02 frin Floating Round To Integer Nearest
FRIN PPC64LE 111111 frt:5 00000 frb:5 01100 010000
# format:X book:I page:167 v2.02 frin Floating Round To Integer Nearest
FRINd PPC64LE 111111 frt:5 00000 frb:5 01100 010001
# format:X book:I page:167 v2.02 frip Floating Round To Integer Plus
FRIP PPC64LE 111111 frt:5 00000 frb:5 01110 010000
# format:X book:I page:167 v2.02 frip Floating Round To Integer Plus
FRIPd PPC64LE 111111 frt:5 00000 frb:5 01110 010001
# format:X book:I page:167 v2.02 friz Floating Round To Integer Zero
FRIZ PPC64LE 111111 frt:5 00000 frb:5 01101 010000
# format:X book:I page:167 v2.02 friz Floating Round To Integer Zero
FRIZd PPC64LE 111111 frt:5 00000 frb:5 01101 010001
# format:X book:I page:160 v:P1 frsp Floating Round to SP
FRSP PPC64LE 111111 frt:5 00000 frb:5 00000011000
# format:X book:I page:160 v:P1 frsp Floating Round to SP
FRSPd PPC64LE 111111 frt:5 00000 frb:5 00000011001
# format:A book:I page:156 PPC frsqrte Floating Reciprocal Square Root Estimate
FRSQRTE PPC64LE 111111 frt:5 00000 frb:5 00000110100
# format:A book:I page:156 PPC frsqrte Floating Reciprocal Square Root Estimate
FRSQRTEd PPC64LE 111111 frt:5 00000 frb:5 00000110101
# format:A book:I page:156 v2.02 frsqrtes Floating Reciprocal Square Root Estimate Single
FRSQRTES PPC64LE 111011 frt:5 00000 frb:5 00000110100
# format:A book:I page:156 v2.02 frsqrtes Floating Reciprocal Square Root Estimate Single
FRSQRTESd PPC64LE 111011 frt:5 00000 frb:5 00000110101
# format:A book:I page:169 PPC fsel Floating Select
FSEL PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 101110
# format:A book:I page:169 PPC fsel Floating Select
FSELd PPC64LE 111111 frt:5 fra:5 frb:5 frc:5 101111
# format:A book:I page:155 P2 fsqrt Floating Square Root
FSQRT PPC64LE 111111 frt:5 00000 frb:5 00000101100
# format:A book:I page:155 P2 fsqrt Floating Square Root
FSQRTd PPC64LE 111111 frt:5 00000 frb:5 00000101101
# format:A book:I page:155 PPC fsqrts Floating Square Root Single
FSQRTS PPC64LE 111011 frt:5 00000 frb:5 00000101100
# format:A book:I page:155 PPC fsqrts Floating Square Root Single
FSQRTSd PPC64LE 111011 frt:5 00000 frb:5 00000101101
# format:A book:I page:153 v:P1 fsub Floating Subtract
FSUB PPC64LE 111111 frt:5 fra:5 frb:5 00000101000
# format:A book:I page:153 v:P1 fsub Floating Subtract
FSUBd PPC64LE 111111 frt:5 fra:5 frb:5 00000101001
# format:A book:I page:153 PPC fsubs Floating Subtract Single
FSUBS PPC64LE 111011 frt:5 fra:5 frb:5 00000101000
# format:A book:I page:153 PPC fsubs Floating Subtract Single
FSUBSd PPC64LE 111011 frt:5 fra:5 frb:5 00000101001
# format:X book:I page:157 v2.06 ftdiv Floating Test for software Divide
FTDIV PPC64LE 111111 bf:3 00 fra:5 frb:5 00100000000
# format:X book:I page:157 v2.06 ftsqrt Floating Test for software Square Root
FTSQRT PPC64LE 111111 bf:3 0000000 frb:5 00101000000
# format:A book:I page:90 v2.03 isel Integer Select
ISEL PPC64LE 011111 rt:5 ra:5 rb:5 bc:5 011110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
# format:D book:I page:48 v:P1 lbz Load Byte & Zero
LBZ PPC64LE 100010 rt:5 ra:5 imm:16 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 32752; } \
!memory { reg_plus_imm($ra, $imm); }
# format:D book:I page:48 v:P1 lbzu Load Byte & Zero with Update
LBZU PPC64LE 100011 rt:5 ra:5 imm:16 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 32752; } \
!memory { reg_plus_imm($ra, $imm); }
# format:X book:I page:49 v:P1 lbzux Load Byte & Zero with Update Indexed
LBZUX PPC64LE 011111 rt:5 ra:5 rb:5 00011101110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:X book:I page:49 v:P1 lbzx Load Byte & Zero Indexed
LBZX PPC64LE 011111 rt:5 ra:5 rb:5 00010101110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:DS book:I page:53 PPC ld Load Dword
LD PPC64LE 111010 rt:5 ra:5 imm:14 00 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 8176; } \
!memory { reg_plus_imm($ra, $imm << 2); }
# format:X book:I page:62 v2.06 ldbrx Load Dword Byte-Reverse Indexed
LDBRX PPC64LE 011111 rt:5 ra:5 rb:5 10000101000 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:X book:I page:54 v3.0 PI ldmx Load Dword Monitored Indexed
LDMX PPC64LE 011111 rt:5 ra:5 rb:5 01001101010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:DS book:I page:53 PPC ldu Load Dword with Update
LDU PPC64LE 111010 rt:5 ra:5 imm:14 01 \
!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 8176; } \
!memory { reg_plus_imm($ra, $imm << 2); }
# format:X book:I page:53 PPC ldux Load Dword with Update Indexed
LDUX PPC64LE 011111 rt:5 ra:5 rb:5 00001101010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:X book:I page:53 PPC ldx Load Dword Indexed
LDX PPC64LE 011111 rt:5 ra:5 rb:5 00000101010 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:D book:I page:143 v:P1 lfd Load Floating Double
LFD PPC64LE 110010 frt:5 ra:5 imm:16 \
!constraints { $ra != 1 && $ra != 13 && $ra != 0 && $imm <= 32752; } \
!memory { reg_plus_imm($ra, $imm); }
# format:DS book:I page:150 v2.05 lfdp Load Floating Double Pair
LFDP PPC64LE 111001 frtp:5 ra:5 imm:14 00 \
!constraints { $frtp % 2 == 0 && $ra > 1 && $ra != 13 && $imm <= 8176; } \
!memory { reg_plus_imm($ra, $imm << 2); }
# format:X book:I page:150 v2.05 lfdpx Load Floating Double Pair Indexed
LFDPX PPC64LE 011111 frtp:5 ra:5 rb:5 11000101110 \
!constraints { $frtp % 2 == 0 && $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:D book:I page:143 v:P1 lfdu Load Floating Double with Update
LFDU PPC64LE 110011 frt:5 ra:5 imm:16 \
!constraints { $ra != 1 && $ra != 13 && $ra != 0 && $imm <= 32752; } \
!memory { reg_plus_imm($ra, $imm); }
# format:X book:I page:143 v:P1 lfdux Load Floating Double with Update Indexed
LFDUX PPC64LE 011111 frt:5 ra:5 rb:5 10011101110 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:X book:I page:143 v:P1 lfdx Load Floating Double Indexed
LFDX PPC64LE 011111 frt:5 ra:5 rb:5 10010101110 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:X book:I page:144 v2.05 lfiwax Load Floating as Integer Word Algebraic Indexed
LFIWAX PPC64LE 011111 frt:5 ra:5 rb:5 11010101110 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:X book:I page:144 v2.06 lfiwzx Load Floating as Integer Word & Zero Indexed
LFIWZX PPC64LE 011111 frt:5 ra:5 rb:5 11011101110 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:D book:I page:142 v:P1 lfs Load Floating Single
LFS PPC64LE 110000 frt:5 ra:5 imm:16 \
!constraints { $ra != 1 && $ra != 13 && $ra != 0 && $imm <= 32752; } \
!memory { reg_plus_imm($ra, $imm); }
# format:D book:I page:142 v:P1 lfsu Load Floating Single with Update
LFSU PPC64LE 110001 frt:5 ra:5 imm:16 \
!constraints { $ra != 1 && $ra != 13 && $ra != 0 && $imm <= 32752; } \
!memory { reg_plus_imm($ra, $imm); }
# format:X book:I page:142 v:P1 lfsux Load Floating Single with Update Indexed
LFSUX PPC64LE 011111 frt:5 ra:5 rb:5 10001101110 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:X book:I page:142 v:P1 lfsx Load Floating Single Indexed
LFSX PPC64LE 011111 frt:5 ra:5 rb:5 10000101110 \
!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \
!memory { reg_plus_reg($ra, $rb); }
# format:D book:I page:50 v:P1 lha Load Hword Algebraic