Computer-Architecture

Index

Lab 1

         FPA : IEEE Single Precision Floating Point Adder with right shifter 
         and recursive doubling CLA.

Lab 2

         FPM : IEEE Single Precision Floating Point Multiplier
         with Barrel shifter components and Wallace Multiplier.

Lab 3

         Design and modeling of processor register file with 32 numbers of 32-bit registers.

Lab 4

         Design and modeling of the Direct Mapped Data Cache Memory. 
         With a block size of 16 Words, Each word is 32-bit. 1024 blocks of Cache.

Lab 5

         Pipeline the 32-bit Integer adder (Recursive doubling based carry lookahead adder)
         designed in the VLSI design Course.

Lab 6

         Pipeline the 32 bit Wallace Tree Multiplier Design 
         that was designed in VLSI Design course
         
         Ensure the stage logic delays matches with the stages of the 
         floating point adder and multiplier, which is designed in next laboratory.

Lab 7

         Pipeline the 32-bit single precision floating point adder.
         
         Ensure the stage logic delays matches with the stages of the 
         floating point adder and multiplier, which is designed in next laboratory.

Lab 8

         Pipeline the 32 bit Single precision floating point Multiplier
         
         Ensure the stage logic delays matches with the stages of the 
         floating point adder and multiplier, which is designed in next laboratory.

Lab 9

         Design 32-bit Logic unit.
         Which can perform
         1) bitwise AND
         2) bitwise XOR
         3) bitwise NAND
         4) bitwise OR
         5) bitwise NOT
         6) bitwise NOR
         7) 2's Complement
         8) bitwise XNOR