The focus of our current research activities is on the design and verification of Embedded Systems and Systems-on-Chip (SoC). We are interested in both the hardware and the low-level software (firmware) of the systems. Some of our research projects are particularly focused on the interaction between hardware and software.
Besides targeting traditional design goals such as high performance and low power consumption, a particular objective of our research is to make contributions to achieving functional safety and security of the designed and manufactured systems. The requirement for functional safety and security is driven by an increased use of embedded systems technology in safety- and security-critical applications such as in avionics and automotive systems (e.g., autonomous cars). Another driver of this research field are new manufacturing techniques in “smart factories” (Industry 4.0) which impose new challenges on the safety of embedded systems technology as well as on the confidentiality of the data being processed. Current research topics are:
- Detection of Security Vulnerabilities in Hardware through exhaustive formal Methods 1234
- Design and Implementation of Mitigations targeting Transient Execution Side Channels and Timing Attacks 56
- Correct-by-Construction Embedded System Design using "Property-First Design" 789
Footnotes
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M.R. Fadiheh, A. Wezel, J. Mueller, J. Bormann, S. Ray, J. Fung, S. Mitra, D. Stoffel, W. Kunz: An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. In IEEE Transactions on Computers, Jan. 2023 ↩
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J. Müller, M.R. Fadiheh, A.L. Duque Antón, T. Eisenbarth, D. Stoffel, W. Kunz: A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level. In Proceedings of the 58th ACM/IEEE Design Automation Conference (DAC '21), Dec. 2021, pp. 991-996 ↩
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L. Deutschmann, J. Müller, M.R. Fadiheh, D. Stoffel, W. Kunz: Towards a formally verified hardware root-of-trust for data-oblivious computing. In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC '22), July 2022, pp. 727–732. ↩
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D. Mehmedagic, M.R. Fadiheh, J. Mueller, A.L. Duque Antón, D. Stoffel, W. Kunz: Design of Access Control Mechanisms in Systems-on-Chip with Formal Integrity Guarantees. In 32nd USENIX Security Conference, 2023 ↩
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T. Jauch, A. Wezel, M.R. Fadiheh, P. Schmitz, S. Ray, J. Fung, C.W. Fletcher, D. Stoffel, W. Kunz: Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov. 2023, pp. 1-9 ↩
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P. Schmitz, T. Jauch, A. Wezel, M.R. Fadiheh, T. Tiemann, J. Heller, T. Eisenbarth, D. Stoffel, W. Kunz: Okapi: A Lightweight Architecture for Secure Speculation Exploiting Locality of Memory Accesses. arXiv preprint, 2023, 2312.08156 (cs.CR) ↩
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T. Ludwig, J. Urdahl, D. Stoffel, W. Kunz: Properties First – Correct-By-Construction RTL Design in System-Level Design Flows. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 11, 2019 ↩
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T. Ludwig, M. Schwarz, J. Urdahl, L. Deutschmann, S. Hetalani, D. Stoffel, W. Kunz: Property Driven Development of a RISC-V CPU. On Proceedings of DVCON US, 2019 ↩
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S. Udupi, J. Urdahl, D. Stoffel, W. Kunz: Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows. In IEEE Transactions on Very Large Scale Integration Systems, Vol. 27, No. 6, June 2019 ↩
