Welcome to the CS Verilog Assignments repository! This repository contains a collection of Verilog code snippets and assignments completed as part of my computer science coursework.
This repository is dedicated to storing Verilog assignments and code snippets completed during my computer science coursework. Each assignment is designed to challenge your understanding of Verilog concepts, including combinational and sequential logic, finite state machines, and more.
- Assignment 1: Half adder using all three models
- Assignment 2: Full adder using all three models
- ...
To get started with the assignments, simply clone this repository to your local machine:
git clone https://github.com/your-username/CS-Verilog-Assignments.gitThen, navigate to the specific assignment directory and explore the Verilog code.
Contributions to this repository are welcome! If you have additional Verilog assignments or improvements to existing ones, feel free to open a pull request.
This repository is unlicensed.
Feel free to use the code in this repository for your own learning purposes. If you find it helpful, please consider giving it a star.