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This is a Xilinx Spartan-3E FPGA application using VGA, for more information see the wiki of the VHDL_application repository
VHDL
Branch: master

README.md

Graphics application using VHDL

Important Note: This repository contains the source codes of a VHDL application dedicated to the Spartan-3E FPGA family.

Intro

The Spartan®-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates.

The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment. The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs.

Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

Xilinx

♦ A Generation Ahead 28nm Process Technology

Xilinx and technology and manufacturing partner Taiwan Semiconductor Manufacturing Company (TSMC) developed a high-κ metal gate (HKMG), high-performance, low-power 28nm process technology for FPGAs. This new 28nm process technology builds upon the achievements of 40nm FPGA process development and introduces a new HKMG technology to maximize usable system performance through lower power.

This technology, although unique in the FPGA industry, is already being embraced by other leading-edge IC suppliers because it dramatically reduces static power when compared with alternative process technologies. At the 28nm node, static power is often a more significant portion of the total power dissipation of a device. Therefore, to achieve maximum power efficiency, the choice of process technology is paramount.

Dramatic reductions in FPGA static power at 28nm leaves more of the system power budget for active, dynamic power, yielding higher levels of both integration and system performance. This gives designers the flexibility to implement products at lower power, or alternatively, create products that increase capacity and performance within the same power budget.

♦ Breakthrough in Optimization and Integration

Five product families with breakthroughs in integration and optimization that change the game in price/performance/watt and enable programmable systems integration. With a broad portfolio of All Programmable FPGAs, SoCs and 3D ICs, you are empowered to maximize system performance, lower power, and reduce BOM costs, while preserving design flexibility across a wide range of markets and applications.

♦ The MIT License

Copyright (c) Samuel Thomas

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

MIT

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