Skip to content
View Satjpatel's full-sized avatar
💭
Great men didn't kill dragons, they rode them.
💭
Great men didn't kill dragons, they rode them.

Highlights

  • Pro

Block or report Satjpatel

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Satjpatel/README.md
  • 👋 Hi, I’m @Satjpatel
  • 👀 I’m interested in Digital Design and Verification!
  • 🌱 I’m currently learning DSP algorithms on FPGAs
  • 💞️ I’m looking to collaborate on FPGA projects
  • 📫 How to reach me: email me at satjpatel007@gmail.com

Pinned Loading

  1. MIPS32 MIPS32 Public

    Basic implementation of MIPS32

    Verilog 3

  2. DSP-Stuff DSP-Stuff Public

    Useful MATLAB Codes

    Python 1

  3. Verilog-HDL-Useful-Codes Verilog-HDL-Useful-Codes Public

    Useful Verilog HDL Codes which can be used in multiple design systems.

    Verilog 4

  4. Digital-Image-Watermarking-and-Its-FPGA-Implementation Digital-Image-Watermarking-and-Its-FPGA-Implementation Public

    My seminar topic as a part of BTech course in ECE. I would be first implementing different schemes of frequency domain watermark embedding and then implement the best one on FPGA.

    VHDL 1 1

  5. NeuralNetworkOnFPGA NeuralNetworkOnFPGA Public

    An initial proof of concept for neural network on FPGA

    SystemVerilog 1

  6. Branch-Predictor-Project Branch-Predictor-Project Public

    Done as a part of CSE-614: Computer Architecture

    C++