MIPS Processor

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A basic MIPS processor implementation in verilog as represented in the following diagram.

Name		Name	Last commit message	Last commit date
Latest commit History 123 Commits
.gitignore		.gitignore
ALU.v		ALU.v
ALU_Control.v		ALU_Control.v
EX_MEM_Reg.v		EX_MEM_Reg.v
EX_PC_Calculation.v		EX_PC_Calculation.v
EX_Stage.v		EX_Stage.v
ID_Control_Unit.v		ID_Control_Unit.v
ID_EX_Reg.v		ID_EX_Reg.v
ID_Register_File.v		ID_Register_File.v
ID_Stage.v		ID_Stage.v
IF_ID_Reg.v		IF_ID_Reg.v
IF_Stage.v		IF_Stage.v
MEM_Data_Memory.v		MEM_Data_Memory.v
MEM_Stage.v		MEM_Stage.v
MEM_WB_Reg.v		MEM_WB_Reg.v
MIPS-AIO.v		MIPS-AIO.v
MIPS.v		MIPS.v
MIPS_testbench.v		MIPS_testbench.v
README.md		README.md
WB_Stage.v		WB_Stage.v
mips.mpf		mips.mpf
test-ALU.v		test-ALU.v
test-EX_PC_Calculation.v		test-EX_PC_Calculation.v
test-EX_Stage.v		test-EX_Stage.v
test-ID_Control_Unit.v		test-ID_Control_Unit.v
test-ID_Stage.v		test-ID_Stage.v
test-IF_Sel.v		test-IF_Sel.v
test-IF_Stage.v		test-IF_Stage.v
test-Register_File		test-Register_File