Capstone Project

Testbench for Embedded 32-bit RISC uProcessor with SDRAM Controller using cocotb

Description

This project provides a testbench implementation for an embedded 32-bit RISC uProcessor with an SDRAM controller using cocotb.

Project Structure

• README.md: This README file providing an overview and guide for the project.
• tests/: Directory containing the testbench module.
• hdl/: Directory containing the RTL code for the uProcessor and SDRAM controller.
• SOC_Design.pdf: Contains the documentation of the IP.

References

Source for the hdl files
Coverage Cookbook from verification academy