cpu.vcd

$date
	Tue Jan 28 04:31:53 2020
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module cpu_tb $end
$var wire 4 ! b [3:0] $end
$var wire 4 " a [3:0] $end
$var reg 1 # clk $end
$var reg 1 $ clr $end
$var reg 16 % code [15:0] $end
$scope module uut $end
$var wire 1 # clk $end
$var wire 1 $ clr $end
$var wire 16 & code [15:0] $end
$var wire 4 ' tmpA [3:0] $end
$var wire 4 ( tmpB [3:0] $end
$var wire 1 ) we $end
$var wire 1 * sub $end
$var wire 2 + rss [1:0] $end
$var wire 4 , opcode [3:0] $end
$var wire 4 - muxRes [3:0] $end
$var wire 1 . dwe $end
$var wire 4 / data [3:0] $end
$var wire 4 0 b [3:0] $end
$var wire 4 1 aluRes [3:0] $end
$var wire 2 2 afs [1:0] $end
$var wire 3 3 addrD [2:0] $end
$var wire 3 4 addrB [2:0] $end
$var wire 3 5 addrA [2:0] $end
$var wire 4 6 a [3:0] $end
$var reg 7 7 instDecoder [6:0] $end
$scope module uud $end
$var wire 4 8 a [3:0] $end
$var wire 2 9 sel [1:0] $end
$var wire 4 : out [3:0] $end
$var wire 4 ; d [3:0] $end
$var wire 4 < c [3:0] $end
$var wire 4 = b [3:0] $end
$upscope $end
$scope module uut $end
$var wire 4 > a [0:3] $end
$var wire 2 ? afs [0:1] $end
$var wire 4 @ b [0:3] $end
$var wire 4 A mux1 [0:3] $end
$var wire 4 B mux2 [0:3] $end
$var wire 4 C mux3 [0:3] $end
$var wire 1 * sub $end
$var wire 4 D xorB [0:3] $end
$var wire 4 E res [0:3] $end
$var wire 4 F mux4 [0:3] $end
$var wire 4 G extendedSub [0:3] $end
$scope module m2 $end
$var wire 4 H a [3:0] $end
$var wire 4 I b [3:0] $end
$var wire 4 J c [3:0] $end
$var wire 4 K d [3:0] $end
$var wire 2 L sel [1:0] $end
$var wire 4 M out [3:0] $end
$upscope $end
$upscope $end
$scope module uut2 $end
$var wire 3 N addrA [2:0] $end
$var wire 3 O addrB [2:0] $end
$var wire 3 P addrD [2:0] $end
$var wire 1 # clk $end
$var wire 1 $ clr $end
$var wire 4 Q data [3:0] $end
$var wire 8 R enable [7:0] $end
$var wire 1 ) load $end
$var wire 8 S decoder [7:0] $end
$var wire 4 T b [3:0] $end
$var wire 4 U a [3:0] $end
$var reg 4 V reg1 [3:0] $end
$var reg 4 W reg2 [3:0] $end
$var reg 4 X reg3 [3:0] $end
$var reg 4 Y reg4 [3:0] $end
$var reg 4 Z reg5 [3:0] $end
$var reg 4 [ reg6 [3:0] $end
$var reg 4 \ reg7 [3:0] $end
$var reg 4 ] reg8 [3:0] $end
$scope module A $end
$var wire 4 ^ In1 [3:0] $end
$var wire 4 _ In2 [3:0] $end
$var wire 4 ` In3 [3:0] $end
$var wire 4 a In4 [3:0] $end
$var wire 4 b In5 [3:0] $end
$var wire 4 c In6 [3:0] $end
$var wire 4 d In7 [3:0] $end
$var wire 4 e In8 [3:0] $end
$var wire 3 f Sel [2:0] $end
$var reg 4 g Out [3:0] $end
$upscope $end
$scope module B $end
$var wire 4 h In1 [3:0] $end
$var wire 4 i In2 [3:0] $end
$var wire 4 j In3 [3:0] $end
$var wire 4 k In4 [3:0] $end
$var wire 4 l In5 [3:0] $end
$var wire 4 m In6 [3:0] $end
$var wire 4 n In7 [3:0] $end
$var wire 4 o In8 [3:0] $end
$var wire 3 p Sel [2:0] $end
$var reg 4 q Out [3:0] $end
$upscope $end
$scope module uut $end
$var wire 3 r in [2:0] $end
$var reg 8 s out [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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