Merge pull request #146 from StanfordVLSI/transmitter

output_buf module create

designs/dragonphy_top/constraints/gen_constraints.py

@@ -61,25 +61,15 @@
 
 # clock dividers
 
-create_generated_clock -name clk_tx_hr_0 \\
-    -source [get_pins itx/qr_mux_4t1_0/div/clkin] \\
+create_generated_clock -name clk_tx_hr \\
+    -source [get_pins itx/div0/clkin] \\
     -divide_by 2 \\
-    [get_pins itx/qr_mux_4t1_0/div/clkout]
+    [get_pins itx/div0/clkout]
 
-create_generated_clock -name clk_tx_hr_1 \\
-    -source [get_pins itx/qr_mux_4t1_1/div/clkin] \\
+create_generated_clock -name clk_tx_qr \\
+    -source [get_pins itx/div1/clkin] \\
     -divide_by 2 \\
-    [get_pins itx/qr_mux_4t1_1/div/clkout]
-
-create_generated_clock -name clk_tx_qr_0 \\
-    -source [get_pins itx/hr_mux_16t4_0/clk_div/clkin] \\
-    -divide_by 2 \\
-    [get_pins itx/hr_mux_16t4_0/clk_div/clkout]
-
-create_generated_clock -name clk_tx_qr_1 \\
-    -source [get_pins itx/hr_mux_16t4_1/clk_div/clkin] \\
-    -divide_by 2 \\
-    [get_pins itx/hr_mux_16t4_1/clk_div/clkout]
+    [get_pins itx/div1/clkout]
 
 #####################
 # clock uncertainty #
@@ -100,16 +90,12 @@
 set_clock_uncertainty -hold 0.01 clk_tx_pi_3
 
 # half rate
-set_clock_uncertainty -setup 0.02 clk_tx_hr_0
-set_clock_uncertainty -hold 0.02 clk_tx_hr_0
-set_clock_uncertainty -setup 0.02 clk_tx_hr_1
-set_clock_uncertainty -hold 0.02 clk_tx_hr_1
+set_clock_uncertainty -setup 0.02 clk_tx_hr
+set_clock_uncertainty -hold 0.02 clk_tx_hr
 
 # quarter rate
-set_clock_uncertainty -setup 0.03 clk_tx_qr_0
-set_clock_uncertainty -hold 0.03 clk_tx_qr_0
-set_clock_uncertainty -setup 0.03 clk_tx_qr_1
-set_clock_uncertainty -hold 0.03 clk_tx_qr_1
+set_clock_uncertainty -setup 0.03 clk_tx_qr
+set_clock_uncertainty -hold 0.03 clk_tx_qr
 
 ################
 # JTAG interface
@@ -156,10 +142,8 @@
         clk_tx_pi_1 \\
         clk_tx_pi_2 \\
         clk_tx_pi_3 \\
-        clk_tx_hr_0 \\
-        clk_tx_hr_1 \\
-        clk_tx_qr_0 \\
-        clk_tx_qr_1 \\
+        clk_tx_hr \\
+        clk_tx_qr \\
     }} \\
     -group {{ clk_retimer clk_main_buf }}
 
@@ -296,10 +280,8 @@
 set_max_transition {0.025*time_scale} -clock_path [get_clock clk_tx_pi_1]
 set_max_transition {0.025*time_scale} -clock_path [get_clock clk_tx_pi_2]
 set_max_transition {0.025*time_scale} -clock_path [get_clock clk_tx_pi_3]
-set_max_transition {0.05*time_scale} -clock_path [get_clock clk_tx_hr_0]
-set_max_transition {0.05*time_scale} -clock_path [get_clock clk_tx_hr_1]
-set_max_transition {0.1*time_scale} -clock_path [get_clock clk_tx_qr_0]
-set_max_transition {0.1*time_scale} -clock_path [get_clock clk_tx_qr_1]
+set_max_transition {0.05*time_scale} -clock_path [get_clock clk_tx_hr]
+set_max_transition {0.1*time_scale} -clock_path [get_clock clk_tx_qr]
 
 # Set transition time for high-speed signals monitored from iacore and itx
 # transition time is 10% of a 4 GHz period.

designs/dragonphy_top/construct.py

@@ -84,6 +84,7 @@ def construct():
             Step( this_dir + '/output_buffer'     ),
             Step( this_dir + '/input_divider' ),
             Step( this_dir + '/phase_interpolator' ),
+            Step( this_dir + '/termination' ),
             Step( this_dir + '/mdll_r1' )
         ]
 
@@ -123,6 +124,7 @@ def construct():
         'output_buffer_lib.db',
         'input_divider_lib.db',
         'phase_interpolator_lib.db',
+        'termination_lib.db',
         'mdll_r1_top_lib.db',
         'sram_tt.db',
         'sram_small_tt.db'
@@ -139,6 +141,7 @@ def construct():
         'output_buffer.lib',
         'input_divider.lib',
         'phase_interpolator.lib',
+        'termination.lib',
         'sram_tt.lib',
         'sram_small_tt.lib'
     ]
@@ -149,6 +152,7 @@ def construct():
         'output_buffer.lef',
         'input_divider.lef',
         'phase_interpolator.lef',
+        'termination.lef',
         'mdll_r1_top.lef',
         'sram.lef',
         'sram_small.lef'
@@ -166,6 +170,7 @@ def construct():
         'output_buffer.gds',
         'input_divider.gds',
         'phase_interpolator.gds',
+        'termination.gds',
         'mdll_r1_top.gds',
         'sram.gds',
         'sram_small.gds'
@@ -177,8 +182,9 @@ def construct():
         'analog_core.spi',
         'mdll_r1_top_macro.cdl',
         'input_buffer.spi',
-        'input_divider.spi',  # TODO: should this be *.lvs.v instead?
-        'phase_interpolator.spi',  # TODO: should this be *.lvs.v instead?
+        'input_divider.spi',
+        'phase_interpolator.spi',
+        'termination.spi',
         'output_buffer.lvs.v',
         'mdll_r1_top.lvs.v',
         'sram.spi',

designs/dragonphy_top/qtm/configure.yml

@@ -44,6 +44,12 @@ commands:
     pt_shell -f ../../input_divider.qtm.tcl
     cd ..
 
+    # build termination (for TX) QTM
+    mkdir -p termination
+    cd termination
+    pt_shell -f ../../termination.qtm.tcl
+    cd ..
+
     # link build products into output folder
     cd ../outputs
     ln -s ../build/analog_core/analog_core_lib.db analog_core_lib.db
@@ -58,6 +64,8 @@ commands:
     ln -s ../build/phase_interpolator/phase_interpolator.lib phase_interpolator.lib
     ln -s ../build/input_divider/input_divider_lib.db input_divider_lib.db
     ln -s ../build/input_divider/input_divider.lib input_divider.lib
+    ln -s ../build/termination/termination_lib.db termination_lib.db
+    ln -s ../build/termination/termination.lib termination.lib
 
 inputs:
   - adk
@@ -75,6 +83,8 @@ outputs:
   - phase_interpolator.lib
   - input_divider_lib.db
   - input_divider.lib
+  - termination_lib.db
+  - termination.lib
 
 parameters:
   # Name of the technology library containing ADK_DRIVING_CELL

designs/dragonphy_top/qtm/termination.qtm.tcl

@@ -0,0 +1,27 @@
+source -echo -verbose ../../inputs/adk/adk.tcl
+read_db ../../inputs/adk/stdcells.db
+
+create_qtm_model termination
+
+set_qtm_global_parameter -param setup -value 0.0
+set_qtm_global_parameter -param hold -value 0.0
+set_qtm_global_parameter -param clk_to_output -value 0.0
+
+set_qtm_technology -library $::env(qtm_tech_lib)
+
+create_qtm_drive_type -lib_cell $ADK_DRIVING_CELL qtm_drive
+create_qtm_load_type -lib_cell $ADK_DRIVING_CELL qtm_load
+
+# define inputs
+set input_list { \
+ VinP \
+ VinN \
+ Vcm \
+}
+create_qtm_port $input_list -type input
+set_qtm_port_load -type qtm_load -factor 2 $input_list
+
+report_qtm_model
+save_qtm_model -format {lib db} -library_cell
+
+exit

designs/dragonphy_top/termination/configure.yml

@@ -0,0 +1,14 @@
+# Adapted from Garnet and ButterPHY
+
+name: termination
+
+commands:
+  - |
+    mkdir -p outputs
+    tar -xzvf /home/sjkim85/dragonphy_tarballs/termination-latest.tar.gz -C outputs
+
+outputs:
+  - termination.lef
+  - termination.gds
+  - termination.spi
+  - termination.version

dragonphy/views.py

@@ -144,6 +144,7 @@ def get_deps_asic(cell_name=None, impl_file=None, process='tsmc16'):
         'analog_core',
         'phase_interpolator',  # used in TX
         'input_divider',  # used in TX
+        'termination',  # used in TX
         'input_buffer',
         'output_buffer',
         'mdll_r1_top',
@@ -155,11 +156,15 @@ def get_deps_asic(cell_name=None, impl_file=None, process='tsmc16'):
     if process == 'freepdk-45nm':
         override['sram'] = 'chip_src_freepdk45'
         override['sram_small'] = 'chip_src_freepdk45'
+        override['tx_tri_buf'] = 'chip_src_freepdk45'
         skip.add('sram_144_1024_freepdk45')
         skip.add('sram_64_256_freepdk45')
+        skip.add('TBUF_X4')
     elif process == 'tsmc16':
         override['sram'] = 'chip_src_tsmc16'
         override['sram_small'] = 'chip_src_tsmc16'
+        override['tx_tri_buf'] = 'chip_src_tsmc16'
+        skip.add('BUFTD4BWP16P90')
         skip.add('TS1N16FFCLLSBLVTC1024X144M4SW')
         skip.add('TS1N16FFCLLSBLVTC256X64M4SW')
     else:

md/tx_intf.md

@@ -19,6 +19,8 @@
 | tx_sel_meas_pi                |         | Nout-1:0               |              | Test         | out      | 0                  |
 | tx_en_inbuf                   |         |                        |              | Test         | out      | 0                  |
 | tx_sel_clk_source             |         |                        |              | Test         | out      | 0                  |
+| tx_ctl_buf_n                  |         | 7:0                    |              | Test         | out      | 0                  |
+| tx_ctl_buf_p                  |         | 7:0                    |              | Test         | out      | 0                  |
 | tx_bypass_inbuf_div           |         |                        |              | Test         | out      | 1                  |
 | tx_bypass_inbuf_div2          |         |                        |              | Test         | out      | 0                  |
 | tx_inbuf_ndiv                 |         | 2:0                    |              | Test         | out      | 0                  |

vlog/chip_src/jtag/jtag.sv

@@ -340,10 +340,15 @@ module jtag (
     assign tdbg_intf_i.en_inbuf_meas = rjtag_intf_i.tx_en_inbuf_meas;
     assign tdbg_intf_i.sel_del_out_pi = rjtag_intf_i.tx_sel_del_out_pi;
     assign tdbg_intf_i.en_del_out_pi = rjtag_intf_i.tx_en_del_out_pi;
-    assign rjtag_intf_i.tx_pm_out_pi = tdbg_intf_i.pm_out_pi;
+    assign tdbg_intf_i.ctl_buf_n = rjtag_intf_i.tx_ctl_buf_n;
+	assign tdbg_intf_i.ctl_buf_p = rjtag_intf_i.tx_ctl_buf_p;
+	assign rjtag_intf_i.tx_pm_out_pi = tdbg_intf_i.pm_out_pi;
     assign rjtag_intf_i.tx_cal_out_pi = tdbg_intf_i.cal_out_pi;
     assign rjtag_intf_i.tx_Qperi = tdbg_intf_i.Qperi;
     assign rjtag_intf_i.tx_max_sel_mux = tdbg_intf_i.max_sel_mux;
+
+
+
 
     // Transmitter data generator
     assign odbg_intf_i.tx_data_gen_rst = rjtag_intf_i.tx_data_gen_rst;

vlog/chip_src/tx_16t1/hr_16t4_mux_top.sv

@@ -6,10 +6,10 @@
 
 module hr_16t4_mux_top (  // The output data rate should be input clock frequency times two.
     input wire logic clk_hr,     // Half rate clock input
+    input wire logic clk_prbs,
     input wire logic [15:0] din,  // Sixteen-bit input data
     input wire logic rst,
-    output wire logic [3:0] dout, // Four-bit output data
-    output wire logic clk_b2 // Divided clk output to drive prbs_gen
+    output wire logic [3:0] dout // Four-bit output data
 );
 
 genvar i;
@@ -19,13 +19,11 @@ generate  // Instantiate 4 hr_4t1_mux_top to form 16:4 mux
             .clk_b(clk_hr),
             .din(din[4*i-1:4*(i-1)]),  // Map 16 bits input to 4 half-rate 4 to 1 mux
             .dout(dout[i-1]),
-            .clk_half(clk_b2)
+            .clk_half(clk_prbs)
         );
     end
 endgenerate
 
-// Clock divider, divide-by-two
-div_b2 clk_div (.clkin(clk_hr), .rst(rst), .clkout(clk_b2));
 
 endmodule
 

vlog/chip_src/tx_16t1/output_buf_tx.sv

@@ -0,0 +1,56 @@
+module output_buf_tx (
+	input wire logic DINN,
+	input wire logic DINP,
+	input wire logic [7:0] CTL_SLICE_N,
+    input wire logic [7:0] CTL_SLICE_P,
+	output wire logic DOUTN,
+    output wire logic DOUTP
+);
+	// Internal connections
+    wire logic BTN; // Buffer to Termination -
+    wire logic BTP; // Buffer to Termination +
+
+
+    // Termination 
+
+
+        termination iBUF_n(
+            .VinP(DOUTN),
+            .VinN(DOUTN),
+            .Vcm(BTN)
+        );
+
+        termination iBUF_p(
+            .VinP(DOUTP),
+            .VinN(DOUTP),
+            .Vcm(BTP)
+        );
+
+
+
+    // instantiate BUFTD +
+
+    generate 
+        for (genvar i=0; i<8; i=i+1) begin: iBUFN
+	        tx_tri_buf i_tri_buf (
+		        // user-provided signals
+		        .DIN(DINN), // Input
+		        .en(CTL_SLICE_N[i]), // Output
+		        .DOUT(BTN) 
+	        );
+        end
+    endgenerate
+
+
+    generate 
+        for (genvar j=0; j<8; j=j+1) begin: iBUFP
+	        tx_tri_buf i_tri_buf (
+		        // user-provided signals
+		        .DIN(DINP), // Input
+		        .en(CTL_SLICE_P[j]), // Output
+		        .DOUT(BTP) 
+	        );
+        end
+    endgenerate
+
+endmodule

vlog/chip_src/tx_16t1/qr_4t1_mux_top.sv

@@ -9,7 +9,6 @@ module qr_4t1_mux_top (
     input wire logic clk_IB, // Four phase clock input from PI+MDLL
     input wire logic [3:0] din,
     input wire logic rst,
-    output wire logic ck_b2,
     output wire logic data
 );
 
@@ -42,7 +41,7 @@ ff_c dff_IB1 (.D(D0DIB), .CP(clk_QB), .Q(D1DIB));
 ff_c dff_IB2 (.D(D1DIB), .CP(clk_QB), .Q(D2MIB));
 
 // 4 to 1 mux
-div_b2 div (.clkin(clk_IB), .rst(rst), .clkout(ck_b2));
+// div_b2 div (.clkin(clk_IB), .rst(rst), .clkout(ck_b2));
 
 assign data = ((clk_Q  & clk_I  & D1MQ ) |
                (clk_I  & clk_QB & D1MI ) |

vlog/chip_src/tx_16t1/tx_debug_intf.sv

@@ -47,8 +47,9 @@ interface tx_debug_intf import const_pack::*; (
 		// Input clock signal measurement
 		logic inbuf_out_meas;								// to output buffer									
 
-
-
+		// output buffer control
+        logic [7:0] ctl_buf_n;
+		logic [7:0] ctl_buf_p;
 
 	modport tx (
 
@@ -82,6 +83,10 @@ interface tx_debug_intf import const_pack::*; (
 		input sel_del_out_pi,
 		input en_del_out_pi,
 
+        // output buf
+        input ctl_buf_n,
+        input ctl_buf_p,
+
         // outputs from analog core
        	output del_out,
        	output pm_out_pi ,
@@ -126,6 +131,10 @@ interface tx_debug_intf import const_pack::*; (
         output sel_del_out_pi,
         output en_del_out_pi,
 
+        // output buf ctl
+        output ctl_buf_n,
+        output ctl_buf_p,
+
         // outputs from analog core
         input del_out,
         input pm_out_pi ,