output_buf module create

[CansWang]

No description provided.

[CansWang]

Just create the output buffer module.

1. Dividers div_b2 that were originally in qr_4t1 and hr_16t4 are moved to tx_top.
2. Interface added for output buffer slice number control. Control bits are 8-bit wide and independent between positive and negative output.

At this point, the buildkite check will definitely fail because the output buffer is a direct instantiation of tsmcN16 std cell logic gate.
Please ignore this temporary. @sgherbst

[sgherbst]

@CansWang thanks for adding these debug signals. Here's how to integrate them into the JTAG interface:

1. Open dragonphy2/md/tx_intf.md and create entries for both signals. The packed dimension for both is 7:0 and the unpacked dimension can be left blank. (This is where you get to specify the default values)
2. Open dragonphy2/vlog/chip_src/jtag/jtag.sv and wire from rjtag_intf_i (which contains all JTAG signals) to tdbg_intf_i (which contains only TX signals). This is where the TX-related wiring is done:
   

   dragonphy2/vlog/chip_src/jtag/jtag.sv

   Lines 317 to 346 in e10cc10

   	// Transmitter
   	assign tdbg_intf_i.en_gf = rjtag_intf_i.tx_en_gf;
   	assign tdbg_intf_i.en_arb_pi = rjtag_intf_i.tx_en_arb_pi;
   	assign tdbg_intf_i.en_delay_pi = rjtag_intf_i.tx_en_delay_pi;
   	assign tdbg_intf_i.en_ext_Qperi = rjtag_intf_i.tx_en_ext_Qperi;
   	assign tdbg_intf_i.en_pm_pi = rjtag_intf_i.tx_en_pm_pi;
   	assign tdbg_intf_i.en_cal_pi = rjtag_intf_i.tx_en_cal_pi;
   	assign tdbg_intf_i.ext_Qperi = rjtag_intf_i.tx_ext_Qperi;
   	assign tdbg_intf_i.sel_pm_sign_pi = rjtag_intf_i.tx_sel_pm_sign_pi;
   	assign tdbg_intf_i.del_inc = rjtag_intf_i.tx_del_inc;
   	assign tdbg_intf_i.enb_unit_pi = rjtag_intf_i.tx_enb_unit_pi;
   	assign tdbg_intf_i.ctl_dcdl_slice = rjtag_intf_i.tx_ctl_dcdl_slice;
   	assign tdbg_intf_i.ctl_dcdl_sw = rjtag_intf_i.tx_ctl_dcdl_sw;
   	assign tdbg_intf_i.ctl_dcdl_clk_encoder = rjtag_intf_i.tx_ctl_dcdl_clk_encoder;
   	assign tdbg_intf_i.disable_state = rjtag_intf_i.tx_disable_state;
   	assign tdbg_intf_i.en_clk_sw = rjtag_intf_i.tx_en_clk_sw;
   	assign tdbg_intf_i.en_meas_pi = rjtag_intf_i.tx_en_meas_pi;
   	assign tdbg_intf_i.sel_meas_pi = rjtag_intf_i.tx_sel_meas_pi;
   	assign tdbg_intf_i.en_inbuf = rjtag_intf_i.tx_en_inbuf;
   	assign tdbg_intf_i.sel_clk_source = rjtag_intf_i.tx_sel_clk_source;
   	assign tdbg_intf_i.bypass_inbuf_div = rjtag_intf_i.tx_bypass_inbuf_div;
   	assign tdbg_intf_i.bypass_inbuf_div2 = rjtag_intf_i.tx_bypass_inbuf_div2;
   	assign tdbg_intf_i.inbuf_ndiv = rjtag_intf_i.tx_inbuf_ndiv;
   	assign tdbg_intf_i.en_inbuf_meas = rjtag_intf_i.tx_en_inbuf_meas;
   	assign tdbg_intf_i.sel_del_out_pi = rjtag_intf_i.tx_sel_del_out_pi;
   	assign tdbg_intf_i.en_del_out_pi = rjtag_intf_i.tx_en_del_out_pi;
   	assign rjtag_intf_i.tx_pm_out_pi = tdbg_intf_i.pm_out_pi;
   	assign rjtag_intf_i.tx_cal_out_pi = tdbg_intf_i.cal_out_pi;
   	assign rjtag_intf_i.tx_Qperi = tdbg_intf_i.Qperi;
   	assign rjtag_intf_i.tx_max_sel_mux = tdbg_intf_i.max_sel_mux;

[sgherbst]

Could you add a behavioral model for the output buffer? That should get tests passing again. You can do this by creating a file vlog/cpu_models/tx_16t1/output_buf_tx.sv and just have it wire from DINN to DOUTN and from DINP to DOUTP. (We can add more detail later). The dependency system should automatically figure out to use that model for CPU-based simulations.

Once that simulation is working, please copy the file to vlog/fpga_models/tx_16t1/output_buf_tx.sv so that it can be used in FPGA emulation. (I may update it later, but this should at least get tests passing again)

[sgherbst]

You don't need the ifndef/endif in this case because we're replacing the output buffer with a model for FPGA emulation

[sgherbst]

please call label this generate block with something like iBUFP and the other one with something like iBUFN; otherwise it will be hard to tell which buffers are P and which are N (might need to know this for PnR scripts)

[sgherbst]

For the tristate buffer, can you try this procedure?

1. Instantiate it as something like tx_tri_buf (i.e., generic gate name)
2. Create an implementation of tx_tri_buf in dragonphy2/vlog/chip_src_tsmc16/tx_16t1/tx_tri_buf . That implementation should instantiate the gate BUFTD4BWP16P90. In other words, it is a wrapper for the process-specific gate.
3. Then, create an implementation of tx_tri_buf in dragonphy2/vlog/chip_src_freepdk45/tx_16t1/tx_tri_buf . That implementation should instantiate an equivalent cell from FreePDK45 -- the options are TBUF_Xn, where n is 1, 2, 4, 8, or 16. Note that for the FreePDK45 cells, the input is called A, the output enable is called EN, and the output is called Z. The reason that we need the FreePDK45 version is because that is what our regression server uses for synthesis tests.
4. Finally, update our dependency management system so that it uses the right view for TSMC16 vs. FreePDK45. Open dragonphy2/dragonphy/views.py and edit this section:
   

   dragonphy2/dragonphy/views.py

   Lines 155 to 166 in e10cc10

   	if process == 'freepdk-45nm':
   	override['sram'] = 'chip_src_freepdk45'
   	override['sram_small'] = 'chip_src_freepdk45'
   	skip.add('sram_144_1024_freepdk45')
   	skip.add('sram_64_256_freepdk45')
   	elif process == 'tsmc16':
   	override['sram'] = 'chip_src_tsmc16'
   	override['sram_small'] = 'chip_src_tsmc16'
   	skip.add('TS1N16FFCLLSBLVTC1024X144M4SW')
   	skip.add('TS1N16FFCLLSBLVTC256X64M4SW')
   	else:
   	raise Exception(f'Unknown process: {process}')

In the freepdk-45nm section, add

override['tx_tri_buf'] = 'chip_src_freepdk45'
skip.add('TBUF_Xn')  # use your value of n (1, 2, 4, 8, or 16)

Similarly, in the tsmc16 section, add

override['tx_tri_buf'] = 'chip_src_tsmc16'
skip.add('BUFTD4BWP16P90')

[sgherbst]

very minor comment -- please delete obsolete code rather than commenting it out

[sgherbst]

@CansWang one last comment -- it looks like this branch is out-of-date with the master branch; would you mind updating it? Thanks!

[sgherbst]

LGTM