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flashchips.c: enable WP for 7 entries of MX chips
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These weren't split:
 * MX25L3206E/MX25L3208E
   Tested: Dasharo#8
 * MX25L6405
 * MX25L6405D
 * MX25L6406E/MX25L6408E
   Tested: Dasharo#8

MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F was split into:
 * MX25L6436E/MX25L6445E/MX25L6465E
   - security register
   - WPS
   - tested: Dasharo#8
 * MX25L6473E
   - security register
   - OTP TB bit in CONFIG/STATUS2 (0x15 opcode)
   - WPS
 * MX25L6473F
   - NO security register
   - OTP TB bit in CONFIG/STATUS2 (0x15 opcode)
   - NO WPS

Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd
Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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@SergiiDmytruk @Sean-StarLabs
SergiiDmytruk authored and Sean-StarLabs committed Feb 20, 2024
1 parent d010d4f commit c4770d4
Showing 1 changed file with 133 additions and 4 deletions.
137 changes: 133 additions & 4 deletions flashchips.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9228,7 +9228,7 @@ const struct flashchip flashchips[] = {
.page_size = 256,
/* OTP: 64B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
.tested = TEST_OK_PREW,
.tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
Expand All @@ -9255,6 +9255,13 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B) and dual I/O supported */
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */
},
.decode_range = DECODE_RANGE_SPI25_BIT_CMP,
},

{
Expand Down Expand Up @@ -9481,6 +9488,12 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B) supported */
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
},
.decode_range = DECODE_RANGE_SPI25,
},

{
Expand Down Expand Up @@ -9517,6 +9530,13 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B), dual I/O read (0xBB) supported */
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */
},
.decode_range = DECODE_RANGE_SPI25_BIT_CMP,
},

{
Expand All @@ -9530,7 +9550,7 @@ const struct flashchip flashchips[] = {
/* MX25L6406E supports SFDP */
/* OTP: 06E 64B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
.tested = TEST_OK_PREW,
.tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
Expand All @@ -9557,19 +9577,121 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B), dual I/O read supported */
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */
},
.decode_range = DECODE_RANGE_SPI25_BIT_CMP,
},

{
.vendor = "Macronix",
.name = "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F",
.name = "MX25L6436E/MX25L6445E/MX25L6465E",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L6405,
.total_size = 8192,
.page_size = 256,
/* supports SFDP */
/* OTP: 512B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_SCUR,
.tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 2048} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 256} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 128} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
.wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */
},
.decode_range = DECODE_RANGE_SPI25_2X_BLOCK,
},

{
.vendor = "Macronix",
.name = "MX25L6473E",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L6405,
.total_size = 8192,
.page_size = 256,
/* supports SFDP */
/* OTP: 512B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_SCUR,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 2048} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 256} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 128} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
.tb = {CONFIG, 3, OTP},
.wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */
},
.decode_range = DECODE_RANGE_SPI25,
},

{
.vendor = "Macronix",
.name = "MX25L6473F",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L6405,
.total_size = 8192,
.page_size = 256,
/* supports SFDP */
/* OTP: 512B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
Expand Down Expand Up @@ -9597,6 +9719,13 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
.tb = {CONFIG, 3, OTP},
},
.decode_range = DECODE_RANGE_SPI25,
},

{
Expand Down

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