Name		Name	Last commit message	Last commit date
Latest commit History 97 Commits
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
Design_version1.pdf		Design_version1.pdf
Project-2-Pipelined-RISC-IITB.pdf		Project-2-Pipelined-RISC-IITB.pdf
README.md		README.md
alu.vhd		alu.vhd
alu2.vhd		alu2.vhd
components_init.vhd		components_init.vhd
components_init.vhd.bak		components_init.vhd.bak
data_extender.vhd		data_extender.vhd
data_extender.vhd.bak		data_extender.vhd.bak
decoder.vhd		decoder.vhd
decoder.vhd.bak		decoder.vhd.bak
execute.vhd		execute.vhd
incrementer_pc.vhd		incrementer_pc.vhd
incrementer_pc.vhd.bak		incrementer_pc.vhd.bak
instruction_decode.vhd		instruction_decode.vhd
instruction_decode.vhd.bak		instruction_decode.vhd.bak
instruction_fetch.qpf		instruction_fetch.qpf
instruction_fetch.qsf		instruction_fetch.qsf
instruction_fetch.vhd		instruction_fetch.vhd
instruction_fetch.vhd.bak		instruction_fetch.vhd.bak
instruction_fetch_nativelink_simulation.rpt		instruction_fetch_nativelink_simulation.rpt
instruction_memory.vhd		instruction_memory.vhd
lm_sm_adder.vhd		lm_sm_adder.vhd
mem_access_stage.vhd		mem_access_stage.vhd
memcomp.vhd		memcomp.vhd
memory.vhd		memory.vhd
memory.vhd.bak		memory.vhd.bak
operand_read.vhd		operand_read.vhd
priority_encoder.vhd		priority_encoder.vhd
priority_encoder.vhd.bak		priority_encoder.vhd.bak
register_1.vhd		register_1.vhd
register_1.vhd.bak		register_1.vhd.bak
register_16.vhd		register_16.vhd
register_16.vhd.bak		register_16.vhd.bak
register_2.vhd		register_2.vhd
register_2.vhd.bak		register_2.vhd.bak
register_3.vhd		register_3.vhd
register_3.vhd.bak		register_3.vhd.bak
register_4.vhd		register_4.vhd
register_4.vhd.bak		register_4.vhd.bak
register_8.vhd		register_8.vhd
register_file.vhd		register_file.vhd
right_shift.vhd		right_shift.vhd
right_shift.vhd.bak		right_shift.vhd.bak
sign_extender_6.vhd		sign_extender_6.vhd
sign_extender_9.vhd		sign_extender_9.vhd
stuff_remaining.txt		stuff_remaining.txt
top_level.vhd		top_level.vhd
writeback.vhd		writeback.vhd

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Pipeline Processor

Designed and implemented a 6 staged pipelined multicycle RISC Processor in VHDL that can perform various arithmetic, logical and branching instructions.
Tested and deployed succesfully on Quartus Prime and DE0-Nano FPGA Board.

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Pipeline Processor

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Pipeline Processor

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