Xilinx Unisim Library

The Xilinx Unisim Library Verilog available as open source under Apache 2.0.

These files coincide with the 2020.1 release of Vivado.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
verilog/src		verilog/src
LICENSE		LICENSE
README.md		README.md

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