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We currently need RTS/CTS to handle flow control between the chip and the FPGA. We can add XON/XOFF, but need extra care for those characters then.
Potentially we can then remove the egress protocol flow control too, the ingress is always needed to be able to send control messages even when the FPGA FIFO is full.
The text was updated successfully, but these errors were encountered:
We currently need RTS/CTS to handle flow control between the chip and the FPGA. We can add XON/XOFF, but need extra care for those characters then.
Potentially we can then remove the egress protocol flow control too, the ingress is always needed to be able to send control messages even when the FPGA FIFO is full.
The text was updated successfully, but these errors were encountered: