OpenLane Yosys Error during synthesize

[akifcelik]

Description

Hi everyone, I am trying to use openlane and skywater pdk to synthesize my ALU design . When start the flow my config.tcl file i get the following error:

[INFO]: Running Synthesis...
[ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /openlane/designs/ALU/runs/RUN_2022.06.28_18.49.22/logs/synthesis/1-synthesis.log |& tee /dev/null"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:

49. Executing ABC pass (technology mapping using ABC).

49.1. Extracting gate netlist of module \divider_64bit_test' to /tmp/yosys-abc-NTqtCv/input.blif'..
Extracted 24759 gates and 24888 wires to a netlist network with 129 inputs and 256 outputs.

49.1.1. Executing ABC.
sh: line 1: 140 Aborted /build/bin/yosys-abc -s -f /tmp/yosys-abc-NTqtCv/abc.script 2>&1
ERROR: ABC: execution of command "/build/bin/yosys-abc -s -f /tmp/yosys-abc-NTqtCv/abc.script 2>&1" failed: return code 134.
child process exited abnormally

[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'designs/ALU/runs/RUN_2022.06.28_18.49.22/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'designs/ALU/runs/RUN_2022.06.28_18.49.22/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.

while executing

"flow_fail"
(procedure "try_catch" line 17)
invoked from within
"try_catch $::env(SYNTH_BIN) -c $::env(SYNTH_SCRIPT) -l [index_file $::env(synthesis_logs)/synthesis.log] |& tee $::env(TERMINAL_OUTPUT)"
(procedure "run_yosys" line 32)
invoked from within
"run_yosys"
(procedure "run_synthesis" line 11)
invoked from within
"[lindex $step_exe 0] [lindex $step_exe 1] "
(procedure "run_non_interactive_mode" line 55)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
if { [info exists arg_values(-file)] } {
run_file [file normalize $a..."
(file "./flow.tcl" line 434)

Environment

python3 ./env.py issue-survey
Kernel: Linux v5.10.16.3-microsoft-standard-WSL2
Distribution: ubuntu 20.04
Python: v3.8.10 (OK)
Container Engine: docker v20.10.16 (OK)
OpenLane Git Version: 8120faaedf752714e65fb7ff91993a8e6630a664
NOT FOUND: Please install pip using your operating system's package manager.
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

8120faa 2022-05-11T19:42:22+02:00 Make `RUN_SPEF_EXTRACTION` skip STA entirely, remove pandas (#1089) - Mohamed Gaber -  (HEAD -> master, tag: 2022.05.12_01.39.47, origin/master, origin/HEAD)
0c611a3 2022-05-09T08:39:57-07:00 Update to use the new C++ pdngen in OR (#1059) - Matt Liberty -  (tag: 2022.05.11_01.53.47)
47c9f22 2022-05-06T14:32:57+02:00 Remove Hard-coded Paths in Sample Designs (#1083) - Balint Cristian -  (tag: 2022.05.07_01.50.30)

Reproduction Material

• List the commands used to run the design.

cd OpenLane
make mount
./flow.tcl -design ALU

Expected behavior

I am expecting some timing slack and violation errors.

Logs

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.12+45 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/multiplier_64bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/multiplier_64bit.v' to AST representation.
Generating RTLIL representation for module `\multiplier_64bit'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/one_bit_to_64_bit_buffer.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/one_bit_to_64_bit_buffer.v' to AST representation.
Generating RTLIL representation for module `\one_bit_to_64_bit_buffer'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/M_TYPE_UNIT.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/M_TYPE_UNIT.v' to AST representation.
Generating RTLIL representation for module `\M_TYPE_UNIT'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/fs_array_64_bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/fs_array_64_bit.v' to AST representation.
Generating RTLIL representation for module `\fs_array_64_bit'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/COMPARATOR_UNIT.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/COMPARATOR_UNIT.v' to AST representation.
Generating RTLIL representation for module `\COMPARATOR_UNIT'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/carry_look_ahaead_generator4_bit_without_last_carry.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/carry_look_ahaead_generator4_bit_without_last_carry.v' to AST representation.
Generating RTLIL representation for module `\carry_look_ahaead_generator4_bit_without_last_carry'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/CLA_adder4_bit_without_carry_out.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/CLA_adder4_bit_without_carry_out.v' to AST representation.
Generating RTLIL representation for module `\CLA_adder4_bit_without_carry_out'.
/openlane/designs/ALU/src/CLA_adder4_bit_without_carry_out.v:33: Warning: Identifier `\C_0' is implicitly declared.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/hs_cell.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/hs_cell.v' to AST representation.
Generating RTLIL representation for module `\hs_cell'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/twos_signed_converter_128bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/twos_signed_converter_128bit.v' to AST representation.
Generating RTLIL representation for module `\twos_signed_converter_128bit'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/Comparator_output_logic.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/Comparator_output_logic.v' to AST representation.
Generating RTLIL representation for module `\Comparator_output_logic'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/half_adder_array_126_bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/half_adder_array_126_bit.v' to AST representation.
Generating RTLIL representation for module `\half_adder_array_126_bit'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/half_adder.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/half_adder.v' to AST representation.
Generating RTLIL representation for module `\half_adder'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/ADDER_SUBTRACTOR_UNIT.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/ADDER_SUBTRACTOR_UNIT.v' to AST representation.
Generating RTLIL representation for module `\ADDER_SUBTRACTOR_UNIT'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/divider_64bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/divider_64bit.v' to AST representation.
Generating RTLIL representation for module `\divider_64bit'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/full_adder.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/full_adder.v' to AST representation.
Generating RTLIL representation for module `\full_adder'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/ALU.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/ALU.v' to AST representation.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/multiplier_adder_row_array_64_bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/multiplier_adder_row_array_64_bit.v' to AST representation.
Generating RTLIL representation for module `\multiplier_adder_row_array_64_bit'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/SHIFTER_UNIT.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/SHIFTER_UNIT.v' to AST representation.
Generating RTLIL representation for module `\SHIFTER_UNIT'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/multiplier_adder_row_array_last_is_half_adder_64_bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/multiplier_adder_row_array_last_is_half_adder_64_bit.v' to AST representation.
Generating RTLIL representation for module `\multiplier_adder_row_array_last_is_half_adder_64_bit'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/Comparator_8_bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/Comparator_8_bit.v' to AST representation.
Generating RTLIL representation for module `\Comparator_8_bit'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/Comparator_64_bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/Comparator_64_bit.v' to AST representation.
Generating RTLIL representation for module `\Comparator_64_bit'.
Successfully finished Verilog frontend.

22. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/mux_4to1.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/mux_4to1.v' to AST representation.
Generating RTLIL representation for module `\mux_4to1'.
Successfully finished Verilog frontend.

23. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/LOGIC_UNIT.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/LOGIC_UNIT.v' to AST representation.
Generating RTLIL representation for module `\LOGIC_UNIT'.
Successfully finished Verilog frontend.

24. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/carry_look_ahaead_generator4_bit_without_pg_and_gg.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/carry_look_ahaead_generator4_bit_without_pg_and_gg.v' to AST representation.
Generating RTLIL representation for module `\carry_look_ahaead_generator4_bit_without_pg_and_gg'.
Successfully finished Verilog frontend.

25. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/twos_signed_converter_64bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/twos_signed_converter_64bit.v' to AST representation.
Generating RTLIL representation for module `\twos_signed_converter_64bit'.
Successfully finished Verilog frontend.

26. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/half_adder_array_62_bit.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/half_adder_array_62_bit.v' to AST representation.
Generating RTLIL representation for module `\half_adder_array_62_bit'.
Successfully finished Verilog frontend.

27. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/CLA_adder_16_bit_without_carry_out.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/CLA_adder_16_bit_without_carry_out.v' to AST representation.
Generating RTLIL representation for module `\CLA_adder_16_bit_without_carry_out'.
Successfully finished Verilog frontend.

28. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/half_subtractor.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/half_subtractor.v' to AST representation.
Generating RTLIL representation for module `\half_subtractor'.
Successfully finished Verilog frontend.

29. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/divider_64bit_test.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/divider_64bit_test.v' to AST representation.
Generating RTLIL representation for module `\divider_64bit_test'.
Successfully finished Verilog frontend.

30. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/one_bit_to_16_bit_buffer.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/one_bit_to_16_bit_buffer.v' to AST representation.
Generating RTLIL representation for module `\one_bit_to_16_bit_buffer'.
Successfully finished Verilog frontend.

31. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/full_subtractor.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/full_subtractor.v' to AST representation.
Generating RTLIL representation for module `\full_subtractor'.
Successfully finished Verilog frontend.

32. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/X_UNIT.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/X_UNIT.v' to AST representation.
Generating RTLIL representation for module `\X_UNIT'.
Successfully finished Verilog frontend.

33. Executing Verilog-2005 frontend: /openlane/designs/ALU/src/fs_cell.v
Parsing SystemVerilog input from `/openlane/designs/ALU/src/fs_cell.v' to AST representation.
Generating RTLIL representation for module `\fs_cell'.
Successfully finished Verilog frontend.

34. Generating Graphviz representation of design.
Writing dot description to `/openlane/designs/ALU/runs/RUN_2022.06.28_18.49.22/tmp/synthesis/hierarchy.dot'.
Dumping module divider_64bit_test to page 1.

35. Executing HIERARCHY pass (managing design hierarchy).

35.1. Analyzing design hierarchy..
Top module:  \divider_64bit_test
Used module:     \divider_64bit
Used module:         \fs_array_64_bit
Used module:             \hs_cell
Used module:                 \half_subtractor
Used module:             \fs_cell
Used module:                 \full_subtractor

35.2. Analyzing design hierarchy..
Top module:  \divider_64bit_test
Used module:     \divider_64bit
Used module:         \fs_array_64_bit
Used module:             \hs_cell
Used module:                 \half_subtractor
Used module:             \fs_cell
Used module:                 \full_subtractor
Removing unused module `\X_UNIT'.
Removing unused module `\one_bit_to_16_bit_buffer'.
Removing unused module `\CLA_adder_16_bit_without_carry_out'.
Removing unused module `\half_adder_array_62_bit'.
Removing unused module `\twos_signed_converter_64bit'.
Removing unused module `\carry_look_ahaead_generator4_bit_without_pg_and_gg'.
Removing unused module `\LOGIC_UNIT'.
Removing unused module `\mux_4to1'.
Removing unused module `\Comparator_64_bit'.
Removing unused module `\Comparator_8_bit'.
Removing unused module `\multiplier_adder_row_array_last_is_half_adder_64_bit'.
Removing unused module `\SHIFTER_UNIT'.
Removing unused module `\multiplier_adder_row_array_64_bit'.
Removing unused module `\full_adder'.
Removing unused module `\ADDER_SUBTRACTOR_UNIT'.
Removing unused module `\half_adder'.
Removing unused module `\half_adder_array_126_bit'.
Removing unused module `\Comparator_output_logic'.
Removing unused module `\twos_signed_converter_128bit'.
Removing unused module `\CLA_adder4_bit_without_carry_out'.
Removing unused module `\carry_look_ahaead_generator4_bit_without_last_carry'.
Removing unused module `\COMPARATOR_UNIT'.
Removing unused module `\M_TYPE_UNIT'.
Removing unused module `\one_bit_to_64_bit_buffer'.
Removing unused module `\multiplier_64bit'.
Removed 25 unused modules.

36. Executing TRIBUF pass.

37. Executing SYNTH pass.

37.1. Executing HIERARCHY pass (managing design hierarchy).

37.1.1. Analyzing design hierarchy..
Top module:  \divider_64bit_test
Used module:     \divider_64bit
Used module:         \fs_array_64_bit
Used module:             \hs_cell
Used module:                 \half_subtractor
Used module:             \fs_cell
Used module:                 \full_subtractor

37.1.2. Analyzing design hierarchy..
Top module:  \divider_64bit_test
Used module:     \divider_64bit
Used module:         \fs_array_64_bit
Used module:             \hs_cell
Used module:                 \half_subtractor
Used module:             \fs_cell
Used module:                 \full_subtractor
Removed 0 unused modules.

37.2. Executing PROC pass (convert processes to netlists).

37.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

37.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/openlane/designs/ALU/src/divider_64bit_test.v:13$4994 in module divider_64bit_test.
Removed a total of 0 dead cases.

37.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

37.2.4. Executing PROC_INIT pass (extract init attributes).

37.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \reset in `\divider_64bit_test.$proc$/openlane/designs/ALU/src/divider_64bit_test.v:13$4994'.
Found VHDL-style edge-trigger \CLK in `\divider_64bit_test.$proc$/openlane/designs/ALU/src/divider_64bit_test.v:13$4994'.

37.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\divider_64bit_test.$proc$/openlane/designs/ALU/src/divider_64bit_test.v:13$4994'.
     1/2: $0\D_reg[63:0]
     2/2: $0\A_reg[63:0]

37.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

37.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\divider_64bit_test.\A_reg' using process `\divider_64bit_test.$proc$/openlane/designs/ALU/src/divider_64bit_test.v:13$4994'.
  created $adff cell `$procdff$5210' with positive edge clock and positive level reset.
Creating register for signal `\divider_64bit_test.\D_reg' using process `\divider_64bit_test.$proc$/openlane/designs/ALU/src/divider_64bit_test.v:13$4994'.
  created $adff cell `$procdff$5211' with positive edge clock and positive level reset.

37.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells).

37.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `divider_64bit_test.$proc$/openlane/designs/ALU/src/divider_64bit_test.v:13$4994'.
Cleaned up 0 empty switches.

37.2.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_subtractor.
Optimizing module fs_cell.
<suppressed ~2 debug messages>
Optimizing module divider_64bit_test.
<suppressed ~2 debug messages>
Optimizing module fs_array_64_bit.
Optimizing module half_subtractor.
Optimizing module divider_64bit.
Optimizing module hs_cell.
<suppressed ~1 debug messages>

37.3. Executing FLATTEN pass (flatten design).
Deleting now unused module full_subtractor.
Deleting now unused module fs_cell.
Deleting now unused module fs_array_64_bit.
Deleting now unused module half_subtractor.
Deleting now unused module divider_64bit.
Deleting now unused module hs_cell.
<suppressed ~131 debug messages>

37.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.
<suppressed ~316 debug messages>

37.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..
Removed 8065 unused cells and 32898 unused wires.
<suppressed ~8194 debug messages>

37.6. Executing CHECK pass (checking for obvious problems).
Checking module divider_64bit_test...
Found and reported 0 problems.

37.7. Executing OPT pass (performing simple optimizations).

37.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \divider_64bit_test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4096 debug messages>

37.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \divider_64bit_test.
Performed a total of 0 changes.

37.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.7.6. Executing OPT_DFF pass (perform DFF optimizations).

37.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.7.9. Finished OPT passes. (There is nothing left to do.)

37.8. Executing FSM pass (extract and optimize FSM).

37.8.1. Executing FSM_DETECT pass (finding FSMs in design).

37.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

37.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

37.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

37.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

37.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

37.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

37.9. Executing OPT pass (performing simple optimizations).

37.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \divider_64bit_test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4096 debug messages>

37.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \divider_64bit_test.
Performed a total of 0 changes.

37.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.9.6. Executing OPT_DFF pass (perform DFF optimizations).

37.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.9.9. Finished OPT passes. (There is nothing left to do.)

37.10. Executing WREDUCE pass (reducing word size of cells).

37.11. Executing PEEPOPT pass (run peephole optimizers).

37.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module divider_64bit_test:
  created 0 $alu and 0 $macc cells.

37.14. Executing SHARE pass (SAT-based resource sharing).

37.15. Executing OPT pass (performing simple optimizations).

37.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \divider_64bit_test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4096 debug messages>

37.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \divider_64bit_test.
Performed a total of 0 changes.

37.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.15.6. Executing OPT_DFF pass (perform DFF optimizations).

37.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.15.9. Finished OPT passes. (There is nothing left to do.)

37.16. Executing MEMORY pass.

37.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

37.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

37.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

37.16.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

37.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.16.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

37.16.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

37.16.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.16.9. Executing MEMORY_COLLECT pass (generating $mem cells).

37.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.18. Executing OPT pass (performing simple optimizations).

37.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.
<suppressed ~128 debug messages>

37.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.18.3. Executing OPT_DFF pass (perform DFF optimizations).

37.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.18.5. Finished fast OPT passes.

37.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

37.20. Executing OPT pass (performing simple optimizations).

37.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \divider_64bit_test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4096 debug messages>

37.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \divider_64bit_test.
Performed a total of 0 changes.

37.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.20.6. Executing OPT_SHARE pass.

37.20.7. Executing OPT_DFF pass (perform DFF optimizations).

37.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.20.10. Finished OPT passes. (There is nothing left to do.)

37.21. Executing TECHMAP pass (map to technology primitives).

37.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

37.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $adff.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~32521 debug messages>

37.22. Executing OPT pass (performing simple optimizations).

37.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.22.3. Executing OPT_DFF pass (perform DFF optimizations).

37.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

37.22.5. Finished fast OPT passes.

37.23. Executing ABC pass (technology mapping using ABC).

37.23.1. Extracting gate netlist of module `\divider_64bit_test' to `<abc-temp-dir>/input.blif'..
Extracted 32450 gates and 32579 wires to a netlist network with 128 inputs and 128 outputs.

37.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

37.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:       63
ABC RESULTS:            ANDNOT cells:     8005
ABC RESULTS:               MUX cells:     4033
ABC RESULTS:              NAND cells:     3843
ABC RESULTS:               NOR cells:       60
ABC RESULTS:               NOT cells:      372
ABC RESULTS:                OR cells:      189
ABC RESULTS:             ORNOT cells:        1
ABC RESULTS:              XNOR cells:     3784
ABC RESULTS:               XOR cells:     4281
ABC RESULTS:        internal signals:    32323
ABC RESULTS:           input signals:      128
ABC RESULTS:          output signals:      128
Removing temp directory.

37.24. Executing OPT pass (performing simple optimizations).

37.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

37.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

37.24.3. Executing OPT_DFF pass (perform DFF optimizations).

37.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..
Removed 0 unused cells and 40899 unused wires.
<suppressed ~24515 debug messages>

37.24.5. Finished fast OPT passes.

37.25. Executing HIERARCHY pass (managing design hierarchy).

37.25.1. Analyzing design hierarchy..
Top module:  \divider_64bit_test

37.25.2. Analyzing design hierarchy..
Top module:  \divider_64bit_test
Removed 0 unused modules.

37.26. Printing statistics.

=== divider_64bit_test ===

   Number of wires:              62018
   Number of wire bits:          95030
   Number of public wires:       37515
   Number of public wire bits:   70527
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              24759
     $_ANDNOT_                    8005
     $_AND_                         63
     $_DFF_PP0_                    128
     $_MUX_                       4033
     $_NAND_                      3843
     $_NOR_                         60
     $_NOT_                        372
     $_ORNOT_                        1
     $_OR_                         189
     $_XNOR_                      3784
     $_XOR_                       4281

37.27. Executing CHECK pass (checking for obvious problems).
Checking module divider_64bit_test...
Found and reported 0 problems.

38. Generating Graphviz representation of design.
Writing dot description to `/openlane/designs/ALU/runs/RUN_2022.06.28_18.49.22/tmp/synthesis/post_techmap.dot'.
Dumping module divider_64bit_test to page 1.

39. Executing SHARE pass (SAT-based resource sharing).

40. Executing OPT pass (performing simple optimizations).

40.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

40.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \divider_64bit_test..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \divider_64bit_test.
Performed a total of 0 changes.

40.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\divider_64bit_test'.
Removed a total of 0 cells.

40.6. Executing OPT_DFF pass (perform DFF optimizations).

40.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..

40.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module divider_64bit_test.

40.9. Finished OPT passes. (There is nothing left to do.)

41. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \divider_64bit_test..
Removed 0 unused cells and 37253 unused wires.
<suppressed ~37253 debug messages>

42. Printing statistics.

=== divider_64bit_test ===

   Number of wires:              24765
   Number of wire bits:          25017
   Number of public wires:         262
   Number of public wire bits:     514
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              24759
     $_ANDNOT_                    8005
     $_AND_                         63
     $_DFF_PP0_                    128
     $_MUX_                       4033
     $_NAND_                      3843
     $_NOR_                         60
     $_NOT_                        372
     $_ORNOT_                        1
     $_OR_                         189
     $_XNOR_                      3784
     $_XOR_                       4281

mapping tbuf

43. Executing TECHMAP pass (map to technology primitives).

43.1. Executing Verilog-2005 frontend: /home/akif/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
Parsing Verilog input from `/home/akif/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.

43.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>

44. Executing SIMPLEMAP pass (map simple cells to gate primitives).

45. Executing TECHMAP pass (map to technology primitives).

45.1. Executing Verilog-2005 frontend: /home/akif/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v
Parsing Verilog input from `/home/akif/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Successfully finished Verilog frontend.

45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

46. Executing SIMPLEMAP pass (map simple cells to gate primitives).

47. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

47.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\divider_64bit_test':
  mapped 128 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_2 cells.

48. Printing statistics.

=== divider_64bit_test ===

   Number of wires:              24893
   Number of wire bits:          25145
   Number of public wires:         262
   Number of public wire bits:     514
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              24887
     $_ANDNOT_                    8005
     $_AND_                         63
     $_MUX_                       4033
     $_NAND_                      3843
     $_NOR_                         60
     $_NOT_                        500
     $_ORNOT_                        1
     $_OR_                         189
     $_XNOR_                      3784
     $_XOR_                       4281
     sky130_fd_sc_hd__dfrtp_2      128

[INFO]: USING STRATEGY AREA 0

49. Executing ABC pass (technology mapping using ABC).

49.1. Extracting gate netlist of module `\divider_64bit_test' to `/tmp/yosys-abc-NTqtCv/input.blif'..
Extracted 24759 gates and 24888 wires to a netlist network with 129 inputs and 256 outputs.

49.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-NTqtCv/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-NTqtCv/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-NTqtCv/input.blif 
ABC: + read_lib -w /openlane/designs/ALU/runs/RUN_2022.06.28_18.49.22/tmp/synthesis/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.06 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Library "sky130A_merged" from "/openlane/designs/ALU/runs/RUN_2022.06.28_18.49.22/tmp/synthesis/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use).  Time =     0.08 sec
ABC: Memory =    7.77 MB. Time =     0.08 sec
ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
ABC: + read_constr -v /openlane/designs/ALU/runs/RUN_2022.06.28_18.49.22/tmp/synthesis/synthesis.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2".
ABC: Setting output load to be 33.442001.
ABC: + read_constr /openlane/designs/ALU/runs/RUN_2022.06.28_18.49.22/tmp/synthesis/synthesis.sdc 
ABC: + fx 
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 10000.0 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + fraig_store 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + fraig_restore 
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: yosys-abc: src/map/amap/amapGraph.c:149: Amap_ManCreateAnd: Assertion `p->nLevelMax < 4094' failed.
ERROR: ABC: execution of command "/build/bin/yosys-abc -s -f /tmp/yosys-abc-NTqtCv/abc.script 2>&1" failed: return code 134.

[vijayank88]

@akifcelik
Have you tried with latest OpenLane git version?

For synthesis issue, you have to provide ALU/src RTL files and config.tcl to debug the issue.

[akifcelik]

Hi,
I have run again with different directory but result unchanged and failed in synthesize.
I have checked following command whether openlane is last version. answer is yes.
akif@DESKTOP-FA8IJ3J:/OpenLane$ git checkout master
Already on 'master'
Your branch is up to date with 'origin/master'.
akif@DESKTOP-FA8IJ3J:/OpenLane$

Project folder with verilog and config.tcl files:
Non_storing_divider.zip

[vijayank88]

@akifcelik
Update config.tcl with set ::env(SYNTH_STRATEGY) {DELAY 1} will pass synthesis stage

[akifcelik]

@vijayank88
Hi ,it has also worked with set ::env(SYNTH_STRATEGY) {AREA 3} .thank you for supporting.

[akifcelik]

Hi , ı have latest Openlane version. I have attached project files to comment on github as a reply. vijayan ***@***.***>, 29 Haz 2022 Çar, 08:13 tarihinde şunu yazdı:

…

@akifcelik <https://github.com/akifcelik> Have you tried with latest OpenLane git version? — Reply to this email directly, view it on GitHub <#1170 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AISPK3M3AR7JJ2MFD6WGKDDVRPLPVANCNFSM52DGUBBA> . You are receiving this because you were mentioned.Message ID: ***@***.***>