PL_TIME_DRIVEN=1 mode is broken

[dineshannayya]

For future searchers: the workaround is to add:

set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_2"

to your design's config.

Original issue as follows:

Time Driven Placement mode is broken in openlane setup (script: or_replace.tcl)

Run fails with below error message,

[INFO ODB-0134] Finished DEF file: input/6-pdn.def
[ERROR STA-0573] 'sky130_fd_sc_hd__inv_1' not found.
Error: 3-verilog2def.sdc, 153 STA-0573

Tools say's not able to find the sky130_fd_sc_hd__inv_1 in trimmed.lib
and inside trimmed.lib this Buffer is commented

/* removed sky130_fd_sc_hd__inv_1 */

This issue is easily reproducible with just adding PL_TIME_DRIVEN=1 in any Efabless example project

Example:
exp12.tar.gz

Also replacing trimmed.lib with sky130_fd_sc_hd__tt_025C_1v80.lib also fails in next stage

[NesterovSolve] Iter: 1 overflow: 0.858753 HPWL: 21743281
[INFO GPL-0100] worst slack 8.59e-09
[INFO GPL-0103] Weighted 2 nets.
[ERROR GPL-0306] RePlAce diverged at wire/density gradient Sum.
Error: or_replace.tcl, 120 GPL-0306

---

[Edit by @donn]

Python: v3.8.10
Kernel: Linux v5.11.0-38-generic
Distribution: ubuntu 20.04
Container Engine: docker v20.10.10
OpenLane Git Version: 2021.10.25_20.35.00
---
PDK Version Verification Status: OK

---
Git Log (Last 5 Commits)

commit 8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
Author: Manar <manarabdelatty@aucegypt.edu>
Date:   Wed Oct 27 08:12:35 2021 -0500

    Update openroad + add multi-corner timing analysis (#680)
    
    * Update OR App
    
    * Fix overflow iterations
    
    * Fix repair_tie_fanout command
    
    * Update design config
    
    * Add multi-corner analysis

commit 683151cc9e601c2f2d774fbcc53cf23060787a41
Author: Vitor Bandeira <vvbandeira@users.noreply.github.com>
Date:   Wed Oct 27 09:36:07 2021 -0300

    Make sure docker logs dir exists (#679)
    
    Signed-off-by: Vitor Bandeira <vitor.vbandeira@gmail.com>
    
    [skip ci]

commit 354a25f7743fe68fa02f6337a922594ac41b7cee
Author: Manar <manarabdelatty@aucegypt.edu>
Date:   Tue Oct 26 09:57:47 2021 -0500

    Update resizer options (#678)
    
    * Update design configuration to address timing violations
    
    * update resizer scripts
    
    - added repair_tie_fanout command
    - added catch to the repair_timing commands to prevent exiting when the utilization limit is reached
    
    * Reset routing_cores to 2

commit c0b75f5f37717201f90396efe835e1978e32dbe6
Author: Anton Blanchard <anton@ozlabs.org>
Date:   Wed Oct 27 00:11:33 2021 +1100

    Fix typo in python exit call (#677)
    
    In commit 4e158a77ef7a ("Quit on timing violations at the typical
    corner (#659)"), os.EX_DATA should have been os.EX_DATAERR.

commit e8f4a88f668b366f126bba40861153bf478a33c1
Author: Donn <me@donn.website>
Date:   Mon Oct 25 20:32:41 2021 +0200

    Last Minute Fixes for MPW3 (#675)

[donn]

To file issues on the OpenLane repository, you need to adhere to the bug report template GitHub provides.

[vijayank88]

@dineshannayya
Provide survey details by using below command in $OPENLANE_FLOW directory
python3 ./env.py issue-survey

@donn
This issue is easily reproducible with just adding PL_TIME_DRIVEN=1 in config.tcl of test designs

[dineshannayya]

@vijayank88 My design is not within Opelane Design folder and it's of Efabless MPW-3 Shuttle directory structure.
As you pointed test fails in any design with just adding PL_TIME_DRIVEN=1 in config.tcl

[donn]

The environment survey does not have much to do with any project in particular. The environment survey shows us your current OpenLane version, a git log, general operating system information and more. It also takes a fraction of a second to run, copy and paste, and lets me do my job much, MUCH easier.

As you've just stated, you're likely running the MPW-3a version of OpenLane. I cannot glean that information from the original post without the environment survey.

[dineshannayya]

@donn Here is the issue survey report generated at my openlane folder.

issue.survey.rpt.gz

[donn]

Thanks, we'll investigate.

[dineshannayya]

I see issue resolved once i update the driving cell from sky130_fd_sc_hd__inv_1 to sky130_fd_sc_hd__inv_2 in the SDC.

Look like new STA tool maybe errors out now for unknown driving cells.

I feel OpenLane's default value of of SYNTH_DRIVING_CELL need to change

set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
                          to
set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_2"

My side issue can be considered closed.

[dralabeing]

@donn looks this issue can be closed with the user suggestion of setting default value for SYNTH_DRIVING_CELL

[vijayank88]

For MPW-3 OpenLane SYNTH_DRIVING_CELL set to sky130_fd_sc_hd__inv_1. Also, sky130_fd_sc_hd__inv_1 is in no_synth_cells list.

Is that root cause for problem?

[dineshannayya]

@vijayank88
Using MPW-3 Openlane , I see generated config file has
set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
Not sure where it controlled the default setting inside the openlane script folder ?

[dralabeing]

@dralabeing @donn as per default setting in Openlane SYNTH_DRIVING_CELL set to sky130_fd_sc_hd__inv_8 sky130_fd_sc_hd__inv_1 is in no_synth_cells list.

For MPW 3 openlane SYNTH_DRIVING_CELL set to sky130_fd_sc_hd__inv_1. Also sky130_fd_sc_hd__inv_1 is in no_synth_cells list.

Is that root cause for problem?

@vijayank88 can you test this with a different setting for the SYNTH_DRIVING_CELL to a cell that is is not in the no_synth_cells list and see if this passes the flow

[dineshannayya]

@dralabeing Yes issue is due the SYNTH_DRIVING_CELL set to sky130_fd_sc_hd__inv_1 and which intern make generated SDC with driving cell set to sky130_fd_sc_hd__inv_1.

Run with PL_TIME_DRIVEN=1 mode fails with below ERROR

[INFO ODB-0134] Finished DEF file: input/6-pdn.def
[ERROR STA-0573] 'sky130_fd_sc_hd__inv_1' not found.
Error: 3-verilog2def.sdc, 153 STA-0573

Issue resolved once i changed the driving cells SDC to sky130_fd_sc_hd__inv_2 or sky130_fd_sc_hd__inv_8

I don't this issue in non PL_TIME_DRIVEN mode.

[vijayank88]

@dralabeing @donn Only this issue comes with caravel platform mpw-3a tag with PL_TIME_DRIVEN=1.
Option 1: Workaround is make this as document

Issue resolved once i changed the driving cells SDC to sky130_fd_sc_hd__inv_2 or sky130_fd_sc_hd__inv_8

Option 2: configuration/README.md:| SYNTH_DRIVING_CELL | The cell to drive the input ports.
(Default: sky130_fd_sc_hd__inv_1)| change it to default sky130_fd_sc_hd__inv_8 as we followed in OpenLane repo.