Added new constraint files for Digulent Arty and Digilent Arty S7 boa…

…rds.

(cherry picked from commit acd48bf28a03ec596619ab71c34f54ac5fa8f5f4)

ucf/Arty/Bus.SPI.xdc

@@ -0,0 +1,23 @@
+##
+## SPI-Bus
+## -----------------------------------------------------------------------------
+##	Bank:						35
+##		VCCO:					3.3V (VCC3V3)
+##	Location:				J6 (2x3 header)
+## -----------------------------------------------------------------------------
+## {OUT}	SerialClock
+set_property PACKAGE_PIN  F1        [ get_ports Arty_SPI_SerialClock ]
+## {OUT}	SlaveSelect
+set_property PACKAGE_PIN  C1        [ get_ports Arty_SPI_SlaveSelect ]
+## {OUT}	MOSI (Master Out - Slave In)
+set_property PACKAGE_PIN  H1        [ get_ports Arty_SPI_MOSI ]
+## {IN}	  MISO (Master In - Slave Out)
+set_property PACKAGE_PIN  G1        [ get_ports Arty_SPI_MISO ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports -regexp {Arty_SPI_.*} ]
+
+# Ignore timings on async I/O pins
+set_false_path								-to		[ get_ports Arty_SPI_SerialClock ]
+set_false_path								-to		[ get_ports Arty_SPI_SlaveSelect ]
+set_false_path								-to		[ get_ports Arty_SPI_MOSI        ]
+set_false_path								-from	[ get_ports Arty_SPI_MISO        ]

ucf/Arty/Clock.SystemClock.xdc

@@ -0,0 +1,26 @@
+## =============================================================================================================================================================
+## Xilinx Design Constraint File (XDC)
+## =============================================================================================================================================================
+##	Board:					Digilent - Arty
+##	FPGA:						Xilinx Artix-7
+##		Device:				XC7A35T
+##		Package:			CSG324
+##		Speedgrade:		-1
+##
+## =============================================================================================================================================================
+## Clock Sources
+## =============================================================================================================================================================
+##
+## System Clock
+## -----------------------------------------------------------------------------
+##		Bank:						35
+##			VCCO:					3.3V (VCC3V3)
+##		Location:				IC2 (ASEM1)
+##			Vendor:				Abracon Corp.
+##			Device:				ASEM1-100.000Mhz-LC-T - 1 to 150 MHz Ultra Miniature Pure Silicon Clock Oscillator
+##			Frequency:		100 MHz, 50ppm
+set_property PACKAGE_PIN    E3        [ get_ports Arty_SystemClock_100MHz ]
+# set I/O standard
+set_property IOSTANDARD     LVCMOS33  [ get_ports Arty_SystemClock_100MHz ]
+# specify a 200 MHz clock
+create_clock -period 10.000 -name PIN_SystemClock_100MHz [ get_ports Arty_SystemClock_100MHz ]

ucf/Arty/GPIO.Button.Special.xdc

@@ -0,0 +1,16 @@
+## =============================================================================================================================================================
+## General Purpose I/O
+## =============================================================================================================================================================
+##
+## Special Buttons
+## -----------------------------------------------------------------------------
+##	Bank:						35
+##		VCCO:					3.3V (VCC3V3)
+##	Location:				BTNR
+## -----------------------------------------------------------------------------
+## {IN}		BTNR; low-active; external 10k pullup resistor
+set_property PACKAGE_PIN  C2        [ get_ports Arty_GPIO_Button_CPU_Reset ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports Arty_GPIO_Button_CPU_Reset ]
+# Ignore timings on async I/O pins
+set_false_path								-from [ get_ports Arty_GPIO_Button_CPU_Reset ]

ucf/Arty/GPIO.LED.RGB.xdc

@@ -0,0 +1,39 @@
+## =============================================================================================================================================================
+## General Purpose I/O
+## =============================================================================================================================================================
+##
+## LEDs
+## -----------------------------------------------------------------------------
+##	Bank:						35
+##		VCCO:					3.3V (FPGA_3V3)
+##	Location:				LD0, LD1, LD2, LD3
+## -----------------------------------------------------------------------------
+## {OUT}	LD0.R;
+set_property PACKAGE_PIN  G6        [ get_ports Arty_GPIO_LED[0]_R ]
+## {OUT}	LD0.G;
+set_property PACKAGE_PIN  F6        [ get_ports Arty_GPIO_LED[0]_G ]
+## {OUT}	LD0.B;
+set_property PACKAGE_PIN  E1        [ get_ports Arty_GPIO_LED[0]_B ]
+## {OUT}	LD1.R;
+set_property PACKAGE_PIN  G3        [ get_ports Arty_GPIO_LED[1]_R ]
+## {OUT}	LD1.G;
+set_property PACKAGE_PIN  J4        [ get_ports Arty_GPIO_LED[1]_G ]
+## {OUT}	LD1.B;
+set_property PACKAGE_PIN  G4        [ get_ports Arty_GPIO_LED[1]_B ]
+## {OUT}	LD2.R;
+set_property PACKAGE_PIN  J3        [ get_ports Arty_GPIO_LED[2]_R ]
+## {OUT}	LD2.G;
+set_property PACKAGE_PIN  J2        [ get_ports Arty_GPIO_LED[2]_G ]
+## {OUT}	LD2.B;
+set_property PACKAGE_PIN  H4        [ get_ports Arty_GPIO_LED[2]_B ]
+## {OUT}	LD3.R;
+set_property PACKAGE_PIN  K1        [ get_ports Arty_GPIO_LED[3]_R ]
+## {OUT}	LD3.G;
+set_property PACKAGE_PIN  H6        [ get_ports Arty_GPIO_LED[3]_G ]
+## {OUT}	LD3.B;
+set_property PACKAGE_PIN  K2        [ get_ports Arty_GPIO_LED[3]_B ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports -regexp {Arty_GPIO_LED\[\d\]_[RGB]} ]
+
+# Ignore timings on async I/O pins
+set_false_path                  -to [ get_ports -regexp {Arty_GPIO_LED\[\d\]_[RGB]} ]

ucf/Arty/GPIO.LED.xdc

@@ -0,0 +1,23 @@
+## =============================================================================================================================================================
+## General Purpose I/O
+## =============================================================================================================================================================
+##
+## LEDs
+## -----------------------------------------------------------------------------
+##	Bank:						35, 14
+##		VCCO:					3.3V (FPGA_3V3)
+##	Location:				LD4, LD5, LD6, LD7
+## -----------------------------------------------------------------------------
+## {OUT}	LD4;
+set_property PACKAGE_PIN  H5        [ get_ports Arty_GPIO_LED[4] ]
+## {OUT}	LD5;
+set_property PACKAGE_PIN  J5        [ get_ports Arty_GPIO_LED[5] ]
+## {OUT}	LD6;
+set_property PACKAGE_PIN  T9        [ get_ports Arty_GPIO_LED[6] ]
+## {OUT}	LD7;
+set_property PACKAGE_PIN  T10       [ get_ports Arty_GPIO_LED[7] ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports -regexp {Arty_GPIO_LED\[\d\]} ]
+
+# Ignore timings on async I/O pins
+set_false_path                  -to [ get_ports -regexp {Arty_GPIO_LED\[\d\]} ]

ucf/Arty/USB_UART.xdc

@@ -0,0 +1,19 @@
+##
+## USB UART
+## -----------------------------------------------------------------------------
+##	Bank:						16
+##		VCCO:					3.3V (VCC3V3)
+##	Location:				IC8
+##		Vendor:				FTDI
+##		Device:				FT2232
+##		Baud-Rate:		300 Bd - 1 MBd
+##	Note:						USB-UART is the master, FPGA is the slave => so TX is an input and RX an output
+## {IN}			{IN}
+set_property PACKAGE_PIN  A9        [ get_ports Arty_USB_UART_TX ]
+## {OUT}		{OUT}
+set_property PACKAGE_PIN  D10       [ get_ports Arty_USB_UART_RX ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports -regexp {Arty_USB_UART_.*} ]
+# Ignore timings on async I/O pins
+set_false_path               -from  [ get_ports Arty_USB_UART_TX ]
+set_false_path               -to    [ get_ports Arty_USB_UART_RX ]

ucf/ArtyS7/Bus.SPI.xdc

@@ -0,0 +1,23 @@
+##
+## SPI-Bus
+## -----------------------------------------------------------------------------
+##	Bank:						15
+##		VCCO:					3.3V (VCC3V3)
+##	Location:				J7 (2x3 header)
+## -----------------------------------------------------------------------------
+## {OUT}	SerialClock
+set_property PACKAGE_PIN  G16       [ get_ports ArtyS7_SPI_SerialClock ]
+## {OUT}	SlaveSelect
+set_property PACKAGE_PIN  H16       [ get_ports ArtyS7_SPI_SlaveSelect ]
+## {OUT}	MOSI (Master Out - Slave In)
+set_property PACKAGE_PIN  H17       [ get_ports ArtyS7_SPI_MOSI ]
+## {IN}	  MISO (Master In - Slave Out)
+set_property PACKAGE_PIN  K14       [ get_ports ArtyS7_SPI_MISO ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports -regexp {ArtyS7_SPI_.*} ]
+
+# Ignore timings on async I/O pins
+set_false_path								-to		[ get_ports ArtyS7_SPI_SerialClock ]
+set_false_path								-to		[ get_ports ArtyS7_SPI_SlaveSelect ]
+set_false_path								-to		[ get_ports ArtyS7_SPI_MOSI        ]
+set_false_path								-from	[ get_ports ArtyS7_SPI_MISO        ]

ucf/ArtyS7/Clock.SystemClock.xdc

@@ -0,0 +1,26 @@
+## =============================================================================================================================================================
+## Xilinx Design Constraint File (XDC)
+## =============================================================================================================================================================
+##	Board:					Digilent - Arty S7
+##	FPGA:						Xilinx Spartan-7
+##		Device:				XC7S50
+##		Package:			CSGA324
+##		Speedgrade:		
+##
+## =============================================================================================================================================================
+## Clock Sources
+## =============================================================================================================================================================
+##
+## System Clock
+## -----------------------------------------------------------------------------
+##		Bank:						15
+##			VCCO:					3.3V (VCC3V3)
+##		Location:				IC2 (ASEM1)
+##			Vendor:				Abracon Corp.
+##			Device:				ASEM1-100.000Mhz-LC-T - 1 to 150 MHz Ultra Miniature Pure Silicon Clock Oscillator
+##			Frequency:		100 MHz, 50ppm
+set_property PACKAGE_PIN    F14       [ get_ports ArtyS7_SystemClock_100MHz ]
+# set I/O standard
+set_property IOSTANDARD     LVCMOS33  [ get_ports ArtyS7_SystemClock_100MHz ]
+# specify a 200 MHz clock
+create_clock -period 10.000 -name PIN_SystemClock_100MHz [ get_ports ArtyS7_SystemClock_100MHz ]

ucf/ArtyS7/GPIO.Button.Special.xdc

@@ -0,0 +1,16 @@
+## =============================================================================================================================================================
+## General Purpose I/O
+## =============================================================================================================================================================
+##
+## Special Buttons
+## -----------------------------------------------------------------------------
+##	Bank:						35
+##		VCCO:					3.3V (VCC3V3)
+##	Location:				BTNR
+## -----------------------------------------------------------------------------
+## {IN}		BTNR; low-active; external 10k pullup resistor
+set_property PACKAGE_PIN  C18       [ get_ports ArtyS7_GPIO_Button_CPU_Reset ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports ArtyS7_GPIO_Button_CPU_Reset ]
+# Ignore timings on async I/O pins
+set_false_path								-from [ get_ports ArtyS7_GPIO_Button_CPU_Reset ]

ucf/ArtyS7/GPIO.LED.RGB.xdc

@@ -0,0 +1,27 @@
+## =============================================================================================================================================================
+## General Purpose I/O
+## =============================================================================================================================================================
+##
+## LEDs
+## -----------------------------------------------------------------------------
+##	Bank:						15
+##		VCCO:					3.3V (FPGA_3V3)
+##	Location:				LD0, LD1
+## -----------------------------------------------------------------------------
+## {OUT}	LD0.R;
+set_property PACKAGE_PIN  J15       [ get_ports ArtyS7_GPIO_LED[0]_R ]
+## {OUT}	LD0.G;
+set_property PACKAGE_PIN  G17       [ get_ports ArtyS7_GPIO_LED[0]_G ]
+## {OUT}	LD0.B;
+set_property PACKAGE_PIN  F15       [ get_ports ArtyS7_GPIO_LED[0]_B ]
+## {OUT}	LD1.R;
+set_property PACKAGE_PIN  E15       [ get_ports ArtyS7_GPIO_LED[1]_R ]
+## {OUT}	LD1.G;
+set_property PACKAGE_PIN  F18       [ get_ports ArtyS7_GPIO_LED[1]_G ]
+## {OUT}	LD1.B;
+set_property PACKAGE_PIN  E14       [ get_ports ArtyS7_GPIO_LED[1]_B ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports -regexp {ArtyS7_GPIO_LED\[\d\]_[RGB]} ]
+
+# Ignore timings on async I/O pins
+set_false_path                  -to [ get_ports -regexp {ArtyS7_GPIO_LED\[\d\]_[RGB]} ]

ucf/ArtyS7/GPIO.LED.xdc

@@ -0,0 +1,23 @@
+## =============================================================================================================================================================
+## General Purpose I/O
+## =============================================================================================================================================================
+##
+## LEDs
+## -----------------------------------------------------------------------------
+##	Bank:						15
+##		VCCO:					3.3V (FPGA_3V3)
+##	Location:				LD2, LD3, LD4, LD5
+## -----------------------------------------------------------------------------
+## {OUT}	LD4;
+set_property PACKAGE_PIN  E18       [ get_ports ArtyS7_GPIO_LED[2] ]
+## {OUT}	LD5;
+set_property PACKAGE_PIN  F13       [ get_ports ArtyS7_GPIO_LED[3] ]
+## {OUT}	LD6;
+set_property PACKAGE_PIN  E13       [ get_ports ArtyS7_GPIO_LED[4] ]
+## {OUT}	LD7;
+set_property PACKAGE_PIN  H15       [ get_ports ArtyS7_GPIO_LED[5] ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports -regexp {ArtyS7_GPIO_LED\[\d\]} ]
+
+# Ignore timings on async I/O pins
+set_false_path                  -to [ get_ports -regexp {ArtyS7_GPIO_LED\[\d\]} ]

ucf/ArtyS7/USB_UART.xdc

@@ -0,0 +1,19 @@
+##
+## USB UART
+## -----------------------------------------------------------------------------
+##	Bank:						14
+##		VCCO:					3.3V (VCC3V3)
+##	Location:				IC9
+##		Vendor:				FTDI
+##		Device:				FT2232
+##		Baud-Rate:		300 Bd - 1 MBd
+##	Note:						USB-UART is the master, FPGA is the slave => so TX is an input and RX an output
+## {IN}			{IN}
+set_property PACKAGE_PIN  V12       [ get_ports ArtyS7_USB_UART_TX ]
+## {OUT}		{OUT}
+set_property PACKAGE_PIN  R12       [ get_ports ArtyS7_USB_UART_RX ]
+# set I/O standard
+set_property IOSTANDARD   LVCMOS33  [ get_ports -regexp {ArtyS7_USB_UART_.*} ]
+# Ignore timings on async I/O pins
+set_false_path               -from  [ get_ports ArtyS7_USB_UART_TX ]
+set_false_path               -to    [ get_ports ArtyS7_USB_UART_RX ]

vhdl_coding.md

@@ -2,7 +2,7 @@
 
 ## Licensing
 PoC is published under the [Apache License, Version 2.0](LICENSE.md).
-Please, make sure you are able and willing to submit your contibutions to
+Please, make sure you are able and willing to submit your contributions to
 this license.
 
 ## Naming
@@ -34,7 +34,7 @@ this license.
 ```vhdl
 -- ===========================================================================
 -- Copyright 2007-2016 Technische Universitaet Dresden - Germany
--- 	     	       Chair for VLSI-Design, Diagnostics and Architecture
+-- 	     	             Chair for VLSI-Design, Diagnostics and Architecture
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -66,7 +66,7 @@ this license.
 3. Use all upper case for constants and generic parameters.
 
 ### Signal Initialization
-1. Specify an initiatilizer for all signals that are to represent sequential
+1. Specify an initializer for all signals that are to represent sequential
    logic, i.e. some state. If their initial state is irrelevant, initialize
    them to a don't-care value as appropriate, e.g. `(others => '-')`. Typically
    the same initial state should be assigned upon a reset condition.