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Clock frequency #134
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Hi Cansu,
The default is to use the analytical models (not characterization). This
will use Cacti-like models for delay and power. Therefore, power is just
alpha*CV^2f. I'm not sure what you mean by "event frequency" value...
…On Mon, Apr 4, 2022 at 9:53 AM Cansu Demirkiran ***@***.***> wrote:
Hi,
I was wondering how we can relate to the maximum possible clock
frequency/memory access latency we can operate the SRAM array using the
timing values shown in the generated datasheet. I noticed that there is an
event frequency value in the tech.py files which is set to 100 MHz. What
does event frequency mean in this context? I tried changing the event
frequency value and observed that the power numbers are scaled linearly but
the timing values stayed the same. I'd greatly appreciate your explanation.
Thanks!
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Thank you for the quick response. Simply, I would like to obtain the information here in this slide, the right hand side plots. Did you obtain these plots in the slides by using characterization? Do you have a documentation for the characterization option, how to use them instead of the default analytical models, etc. For your question, the event frequency is defined in the tech files (example) Thanks! |
Hi, We ran that manually using some bash scripts. Matt |
Hi,
I was wondering how we can relate to the maximum possible clock frequency/memory access latency we can operate the SRAM array using the timing values shown in the generated datasheet. I noticed that there is an event frequency value in the tech.py files which is set to 100 MHz. What does event frequency mean in this context? I tried changing the event frequency value and observed that the power numbers are scaled linearly but the timing values stayed the same. I'd greatly appreciate your explanation. Thanks!
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