Courseworks of CMOS VLSI design using Cadence Virtuoso in AMI 0.60u C5N technology and verifications using Verilog.
Component includes schematics and layouts of basic logic component like logic gates, adder, and multiplier.
Lab includes reports of design and simulation of basic logic component.
Final_Project includes schematics, layouts, simulation, GDS file, and report of my final project: Convolutional Computation Unit, which is capable of doing 2-D convolution with 4-bit uint input data and 1x3 uint kernel in 55MHz.
