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Regression? It fails to handle tristate buffer properly. #128

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elfmimi opened this Issue Oct 4, 2018 · 1 comment

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@elfmimi
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elfmimi commented Oct 4, 2018

Simplified code like this ...

module bootloader (
inout pin_usbp,
inout pin_usbn,
...
);
wire usb_p_tx;
wire usb_n_tx;
wire usb_p_rx;
wire usb_n_rx;
wire usb_tx_en;

assign pin_usbp = usb_tx_en ? usb_p_tx : 1'bz;
assign pin_usbn = usb_tx_en ? usb_n_tx : 1'bz;
assign usb_p_rx = usb_tx_en ? 1'b1 : pin_usbp;
assign usb_n_rx = usb_tx_en ? 1'b0 : pin_usbn;
endmodule

generates an error like this.

fatal error: Top level port 'pin_usbp' assigned to an IO pad 'Y' and internal nodes

Cf. tinyfpga/TinyFPGA-Bootloader#29

I don't know which side is responsible for fixing the issue.

@Wren6991

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Wren6991 commented Nov 27, 2018

Same failure here, with similar-looking code.

My yosys version:

Yosys 0.8+23 (git sha1 db676957, gcc 8.2.0-7ubuntu1 -fPIC -O2)

arachne-pnr:

arachne-pnr 0.1+325+0 (git sha1 840bdfd, g++ 8.2.0-7ubuntu1 -O2)

So both fairly recent builds from github master.

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