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My question is if there is a way to access the submodule signals from the testbench itself?
Essentially, what I would like to do is something like:
if (!reset) assert (uut.state!=3);
If I try it like this, what I get is the following warning
Warning: Identifier `\uut.state' is implicitly declared.
and the assertion is ignored during the proof.
The two workarounds I tried were
Putting the assertion directly into the demo module
Creating a separate output for the state signal
Both of them worked. For my use case, however, I would like to compare the signals of the different submodules. Therefore, only the second option would be viable.
However, creating a separate output for each signal I want to compare seems very cumbersome, so I would like to know if hierarchical access is also possible somehow?
The text was updated successfully, but these errors were encountered:
No, unfortunately hierarchical access is only possible using the verific frontend (available in the commercial Tabby CAD Suite only). There is an effort to implement it for read_verilog by an external contributor but it seems currently stalled: YosysHQ/yosys#2752
Hello everyone,
I was playing around with the unbounded prover example:
My question is if there is a way to access the submodule signals from the testbench itself?
Essentially, what I would like to do is something like:
If I try it like this, what I get is the following warning
and the assertion is ignored during the proof.
The two workarounds I tried were
Both of them worked. For my use case, however, I would like to compare the signals of the different submodules. Therefore, only the second option would be viable.
However, creating a separate output for each signal I want to compare seems very cumbersome, so I would like to know if hierarchical access is also possible somehow?
The text was updated successfully, but these errors were encountered: