Yosys modulus operator has remainder semantics

[pepijndevos]

As per Wikipedia, usually modulus has the sign of the divisor, while remainder has the sign of the dividend. In languages that only have one % operator, you can get either behavior. https://en.wikipedia.org/wiki/Modulo_operation#In_programming_languages

However, VHDL is a language that has both a mod and a rem operator, where rem has the behavior of Yosys/Verilog $mod/%, and there is no way to represent actual VHDL mod.

Below is a program that when synthesized with GHDL currently throws an error. When using Verific, both statements result in a $mod operator, which is clearly incorrect.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lut2 is
    port (a: in integer;
          b: in integer;
          y: out integer;
          z: out integer);
end lut2;

architecture synth of lut2 is
begin
  y <= a mod b;
  z <= a rem b;
end synth;

Here is the offending Verific code:

yosys/frontends/verific/verific.cc

Lines 483 to 487 in db22687

	if (inst->Type() == OPER_MODULO) {
	cell = module->addMod(inst_name, IN1, IN2, OUT, SIGNED);
	import_attributes(cell->attributes, inst);
	return true;
	}

[whitequark]

I have the same problem in nMigen, which follows Python semantics and so uses a modulo operator. IMO the $mod cell should be renamed to $rem, and a new $mod (or perhaps $mod2) cell should be added with the correct semantics, so that it can be used by VHDL and nMigen.