assert in write_cxxrtl

[galibert]

m68k.v is the result of sv2v on fx68k

Do:
read -vlog95 m68k.v
hierarchy -top fx68k
write_cxxrtl m68k.cc

The write_cxxrtl step asserts in dump_sigchunk with a WireType::UNUSED that is not lhs.
ERROR: Assert `is_lhs' failed in backends/cxxrtl/cxxrtl_backend.cc:897.

m68k.zip

[galibert]

mem.zip
Missing mem files

[Lunaphied]

I've looked at this a bit and the issue appears to be that during write_cxxrtl it detects the wire as unused at optimization level -O5 or above. Those allow "public" wires (iirc this is Yosys slang for "named in the design but not an output), to be marked as LOCAL which means they're not exposed outside the eval() method for CXXRTL.

This later leads to the wire in question (in this case nDecoder.pcRelDbl) being marked as UNUSED because it ends up being able to be totally optimized out of the design (not 100% sure about the details on how that optimization takes place, but I'm assuming it's valid and that the tree of wires it connects to eventually terminates as unused).

Because the wire is UNUSED, this means that nothing should assign to it ever leading to the reason for the failing assert to exist. However, during -g4 (the highest debug info setting), debug info is created for all public signals in the design, including those that are optimized out. In order to do this it actually generates a secondary eval() method that includes such unoptimized signals in the design, running through the passes but with for_debug = true.

This shouldn't fail because theoretically there's a separate WireType mapping for the wires in debug mode, where UNUSED should be mapped to something else. Unfortunately, this doesn't occur, leading a wire in the debug version of the design that hasn't had it's type changed for eval_debug. This happens because not only do public debug visible wires have to be reintroduced, so does the entire tree of downstream connections.

The debug code basically re-runs the liveness check used before, but allowing OUTLINE (public wires visible only for debug) to be considered live as well, then assigns debug specific types to wires that are normally optimized out, but are used in the computation of other public signals.

I think the actual issue is the use of || instead of && here

yosys/backends/cxxrtl/cxxrtl_backend.cc

Line 2650 in 01626e6

if (live_wires[wire].empty() || debug_live_wires[wire].empty()) {

Since some wires will be in one set but not the other, and that check actually tests for the wire being unused in both sets. Patching that seems to resolve the issue and I'll submit a PR.