CXXRTL: internal assertion when calling write_cxxrtl on minimised testcase

[Wren6991]

Steps to reproduce the issue

See comments on #2881. File bug.il:

# Generated by Yosys 0.9+4081 (git sha1 9af88951b, clang 10.0.0-4ubuntu1 -fPIC -Os)
autoidx 143
attribute \src "/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:18.1-115.10"
attribute \cells_not_processed 1
attribute \dynports 1
module \hazard3_alu
  parameter \W_DATA 32
  attribute \src "/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:0.0-0.0"
  wire $0\msb$func$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:42$3.$result[0:0]$41
  attribute \src "/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:39.26-39.61"
  wire width 32 $add$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:39$14_Y
  attribute \src "/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:0.0-0.0"
  wire \msb$func$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:42$3.$result
  attribute \src "/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:39.19-39.22"
  wire width 32 \sum
  attribute \src "/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:39.26-39.61"
  cell $add $add$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:39$14
    parameter \A_SIGNED 0
    parameter \A_WIDTH 32
    parameter \B_SIGNED 0
    parameter \B_WIDTH 1
    parameter \Y_WIDTH 32
    connect \A 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
    connect \B 1'x
    connect \Y $add$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:39$14_Y
  end
  attribute \src "/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:0.0-0.0"
  process $proc$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:0$40
    assign $0\msb$func$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:42$3.$result[0:0]$41 \sum [31]
    sync always
      update \msb$func$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:42$3.$result $0\msb$func$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:42$3.$result[0:0]$41
  end
  connect \sum $add$/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:39$14_Y
end

Run:

yosys -p "read_ilang bug.il; write_cxxrtl dut.cpp"

Expected behavior

Either write out a .cpp file, or respond with an error about some issue with the RTL

Actual behavior

Trips an internal assertion in the CXXRTL backend:

ERROR: Assert `!is_lhs' failed in backends/cxxrtl/cxxrtl_backend.cc:969.

(removed some other notes that are now covered by #2883)

[Wren6991]

Bisecting changes points to efc4327 which changes code close to the assert that fires on the unreduced source, Assert 'flow.wire_comb_defs[it].size() == 1'

If I checkout efc4327 and restore this line that was removed by that commit:

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index dfdb9df74..cec5dc0a5 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -2794,6 +2794,7 @@ struct CxxrtlWorker {
                                for (auto wire : module->wires()) {
                                        const auto &wire_type = wire_types[wire];
                                        auto &debug_wire_type = debug_wire_types[wire];
+                                       if (wire_type.type == WireType::UNUSED) continue;
 
                                        if (!debug_info) continue;
                                        if (wire->port_input || wire_type.is_buffered())

Then I do not trip the above assertions. However I don't understand the code enough to know why this is.

edit: following this I could reduce further and have now opened a second issue #2883 for that assertion