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Interfacing to Xilinx Vivado block design environment #26

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Interfacing to Xilinx Vivado block design environment #26

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Commits on Mar 27, 2020

  1. fix aximrd2wbsp.v parameters AW. fix S_AXI_ARREADY output wire

    @motylewski
    motylewski committed Mar 27, 2020
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Commits on Jul 21, 2020

  1. ported wb2axip to Xilinx Vivado Verilog (not SystemVerilog because im… 

    …port in block design does not work in 2019.2) replaced localparam, removed default_nettype none
    @motylewski
    motylewski committed Jul 21, 2020
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Commits on Jul 27, 2020

  1. fixed default_nettype in all wb2axip modules

    @motylewski
    motylewski committed Jul 27, 2020
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Commits on Jul 28, 2020

  1. added X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" to… 

    … module axim2wbsp
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    motylewski committed Jul 28, 2020
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Commits on Aug 1, 2020

  1. added X_INTERFACE_INFOattributes for automatic AXI bus detection in V… 

    …ivado
    @motylewski
    motylewski committed Aug 1, 2020
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Commits on Aug 6, 2020

  1. added ifndef YOSYS default_wiretype to 2 files

    @motylewski
    motylewski committed Aug 6, 2020
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Commits on Aug 7, 2020

  1. propagated AXI_LSBS to submodules because I need to override it

    @motylewski
    motylewski committed Aug 7, 2020
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  2. Added IP-XACT definitions of Wishbone3 and Wishbone4 bus. Added X_INT… 

    …ERFACE_INFO wishbone4 to wbp2classic to use the module in Xilinx Vivado block design
    @motylewski
    motylewski committed Aug 7, 2020
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  3. merge changes accumulated in master since Mar 10 2020 with IP-XACT in… 

    …terface definitions
    @motylewski
    motylewski committed Aug 7, 2020
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Commits on Aug 10, 2020

  1. pulling from upstream ZipCPU

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    motylewski committed Aug 10, 2020
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Commits on Aug 11, 2020

  1. merge issue 25 fixes and added OPT_SWAP_ENDIANNESS to axim2wbsp.v

    @motylewski
    motylewski committed Aug 11, 2020
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  2. prepared for upstream merge, cleaned up module interfaces

    @motylewski
    motylewski committed Aug 11, 2020
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Commits on Aug 13, 2020

  1. Merge remote-tracking branch 'upstream/master'

    @motylewski
    motylewski committed Aug 13, 2020
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  2. split lines with X_INTERFACE_INFO as requested for upstream merge

    @motylewski
    motylewski committed Aug 13, 2020
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Commits on Aug 17, 2020

  1. changed wishbone interface name B3 and B4

    @motylewski
    motylewski committed Aug 17, 2020
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  2. STALL input is required in B4 master

    @motylewski
    motylewski committed Aug 17, 2020
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