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Interfacing to Xilinx Vivado block design environment #26

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Interfacing to Xilinx Vivado block design environment #26

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476d1d4
fix aximrd2wbsp.v parameters AW. fix S_AXI_ARREADY output wire
motylewski Mar 27, 2020
7a65816
ported wb2axip to Xilinx Vivado Verilog (not SystemVerilog because im…
motylewski Jul 21, 2020
ae28882
fixed default_nettype in all wb2axip modules
motylewski Jul 27, 2020
64f8741
added X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" to…
motylewski Jul 28, 2020
ed01204
added X_INTERFACE_INFOattributes for automatic AXI bus detection in…
motylewski Aug 1, 2020
750887f
added ifndef YOSYS default_wiretype to 2 files
motylewski Aug 6, 2020
3d1bc5d
propagated AXI_LSBS to submodules because I need to override it
motylewski Aug 7, 2020
75db1f2
Added IP-XACT definitions of Wishbone3 and Wishbone4 bus. Added X_INT…
motylewski Aug 7, 2020
264681f
merge changes accumulated in master since Mar 10 2020 with IP-XACT i…
motylewski Aug 7, 2020
c13293a
pulling from upstream ZipCPU
motylewski Aug 10, 2020
460af60
merge issue 25 fixes and added OPT_SWAP_ENDIANNESS to axim2wbsp.v
motylewski Aug 11, 2020
57414d3
prepared for upstream merge, cleaned up module interfaces
motylewski Aug 11, 2020
5a7cfa3
Merge remote-tracking branch 'upstream/master'
motylewski Aug 13, 2020
bdc5125
split lines with X_INTERFACE_INFO as requested for upstream merge
motylewski Aug 13, 2020
a770ac1
changed wishbone interface name B3 and B4
motylewski Aug 17, 2020
a7264fc
STALL input is required in B4 master
motylewski Aug 17, 2020
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17 changes: 17 additions & 0 deletions interfaces/wishboneB3.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>bus</spirit:library>
<spirit:name>wishbone</spirit:name>
<spirit:version>B3</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:description>wishbone from opencores.org b3.pdf</spirit:description>
<spirit:vendorExtensions>
<xilinx:busDefinitionInfo>
<xilinx:displayName>wishbone</xilinx:displayName>
</xilinx:busDefinitionInfo>
</spirit:vendorExtensions>
</spirit:busDefinition>
251 changes: 251 additions & 0 deletions interfaces/wishboneB3_rtl.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>bus</spirit:library>
<spirit:name>wishbone_rtl</spirit:name>
<spirit:version>B3</spirit:version>
<spirit:busType spirit:vendor="opencores.org" spirit:library="bus" spirit:name="wishbone" spirit:version="B3"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>CYC</spirit:logicalName>
<spirit:description>cycle in progress</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isAddress>true</spirit:isAddress>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>STB</spirit:logicalName>
<spirit:description>data transfer strobe RD or WR</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>WE</spirit:logicalName>
<spirit:description>WriteEnable</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SEL</spirit:logicalName>
<spirit:description>select sub-words e.g. bytes for writing</spirit:description>
<spirit:wire>
<spirit:onMaster/>
<spirit:onSlave>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>65535</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>ACK</spirit:logicalName>
<spirit:description>ACK master input</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>ADR</spirit:logicalName>
<spirit:description>Address bus</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isAddress>true</spirit:isAddress>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:abstractionDefinitionPortInfo>
<xilinx:group>addr</xilinx:group>
</xilinx:abstractionDefinitionPortInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
<spirit:logicalName>DAT_MISO</spirit:logicalName>
<spirit:description>DAT_I master O slave</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isData>true</spirit:isData>
</spirit:qualifier>
<spirit:onMaster>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>DAT_MOSI</spirit:logicalName>
<spirit:description>DAT_O master I slave</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave/>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>LOCK</spirit:logicalName>
<spirit:description>uninterruptible access</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>ERR</spirit:logicalName>
<spirit:description>slave terminates access with error</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>RTY</spirit:logicalName>
<spirit:description>slave not ready, access terminated</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>TGD_MISO</spirit:logicalName>
<spirit:description>information that is associated with the data input array [DAT_I()], and is qualified by signal [STB_I]</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>TGD_MOSI</spirit:logicalName>
<spirit:description>info about data output array [DAT_O()], and is qualified by signal [STB_O]</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isData>true</spirit:isData>
</spirit:qualifier>
<spirit:onSlave>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>TGA</spirit:logicalName>
<spirit:description>address lines [ADR_O()] info</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isAddress>true</spirit:isAddress>
</spirit:qualifier>
<spirit:onSlave>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>TGC</spirit:logicalName>
<spirit:description>bus cycles, qualified by [CYC_O]</spirit:description>
<spirit:wire>
<spirit:onSlave>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CTI</spirit:logicalName>
<spirit:description>CTI</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:width>3</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>3</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>BTE</spirit:logicalName>
<spirit:description>BTE</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:width>2</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>2</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:vendorExtensions>
<xilinx:abstractionDefinitionInfo>
<xilinx:displayName>wishbone</xilinx:displayName>
</xilinx:abstractionDefinitionInfo>
</spirit:vendorExtensions>
</spirit:abstractionDefinition>
18 changes: 18 additions & 0 deletions interfaces/wishboneB4.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>bus</spirit:library>
<spirit:name>wishbone</spirit:name>
<spirit:version>B4</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:extends spirit:vendor="opencores.org" spirit:library="bus" spirit:name="wishbone" spirit:version="B3"/>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:description>https://opencores.org/howto/wishbone 2010-06-22 Rev.B4 specs.</spirit:description>
<spirit:vendorExtensions>
<xilinx:busDefinitionInfo>
<xilinx:displayName>wishbone</xilinx:displayName>
</xilinx:busDefinitionInfo>
</spirit:vendorExtensions>
</spirit:busDefinition>
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