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Updated core file
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Me committed Sep 21, 2016
1 parent 9258deb commit 204a8bd
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions wbicapetwo.core
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Original file line number Diff line number Diff line change
Expand Up @@ -2,12 +2,12 @@ CAPI=1
[main]
description = "Wishbone to ICAPE2 interface conversion"

[verilog]
src_files = rtl/wbicapetwo.v
[fileset rtl]
files = rtl/wbicapetwo.v
file_type = verilogSource

[provider]
name=github
user=ZipCPU
repo=wbicapetwo
version = master
cachable = true

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