riscv_opcode_tidying_1

Cleaning: Opcode Tidying (Batch 1)

• Branch: riscv-opcode-tidying-1
• Tracking PR: #14 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-07-09)
  • PATCH v2 (2022-10-19)
    • PING^1 (2022-11-05)
  • PATCH v3 (2022-11-15)
  • PATCH v4 (2022-11-18)

Conflicts With

• Upcoming (Pending): Disassembler: Support special (non-standard) encodings
  It also touches definition of fence.i.
• RISC-V: Add INSN_DREF to memory read/write instructions
  It also touches definition of some T-Head custom instructions.

Issue Solved

It refines the code so that latest names are primarily used. It also removes unused instructions.