riscv_opcode_tidying_hints_1

Cleaning: Opcode Tidying (Hints)

• Status: Merged for Binutils 2.40
• Branch: riscv-opcode-tidying-hints-1
• Tracking PR: #68 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-10-08)

Issue Solved

This is another small tidying patchset.

Because of the scanning process of the RISC-V disassembler, all standard hints must be placed before corresponding instruction.

In the past, prefetch.[irw] (from Zicbop) hints are placed just before ORI and pause (from Zihintpause) is placed just before FENCE. It's not bad but will force the developer to taint basic instructions section.

Considering upcoming Zihintntl standard hints will be a bit more complex than the current hints (some can be a part of either ADD or C.ADD) and the disassembler is fine as long as a hint instruction is placed before the base instruction (no need them to be adjacent), I think moving all standard hints before all real instructions might improve the readability and won't disrupt the indentation of basic instructions anymore.