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1. MIPS-Processor MIPS-Processor Public

   Complete design of a 32-bit 5-stage pipelined MIPS Processor with an L1 cache with snoopy coherency with achieved Gate-level Frequency of 53MHz and fully synthesised on an FPGA

   SystemVerilog 1

2. SRAM-DESIGN SRAM-DESIGN Public

   SRAM Design

   1

3. ASIC-Components-Design ASIC-Components-Design Public

   RTL designs of sub-level ASIC components in System-verilog, with tests and verification testbenches for both simulation and synthesis.

   Verilog

4. vortex vortex Public

   Forked from vortexgpgpu/vortex

   Verilog

5. AWS-Weather-Interface AWS-Weather-Interface Public

   Implementation of Weather Monitoring Interface using Flask Framework working in tandem is AWS. Features IAM user account capabilities with sign up, location specific tracking and data downloads.

   CSS

6. CUDA-Heat-Algorithm CUDA-Heat-Algorithm Public

   Heat plate algorithm for calculating the heat dispersal. Using CUDA for optimisation and running on GPUs with threads

   C