Review what happens when OUTBOX is full

[adumont]

When OUTBOX is full, FSM waits (#12).
Confirm that when we pop an item out (cpu_out_rd=1):

• Outbox should clear the outbox full signal
• FSM will resume activity

[adumont]

try using w_full_n instead of o_err as FIFO full flag.
(note: w_full_n doesn't seem to be negative logic deespite the _n... It becomes 1 when the FIFO gets full, and 0 again when it gets freed).

[adumont]

Also review ZipCPU/wbuart32#3 (comment) :

you are using the wrong signal to know if the FIFO is full or now. The err signal is set if you actually overflow the FIFO, and then cleared when you reset the FIFO to acknowledge the error--just as you noticed.

To know if the FIFO is actually full, you need to check the bottom bit of the status register, o_status. On a receive FIFO, where RXFIFO == 1'b1, this will be true if anything is within the FIFO that may then be read. For a transmit FIFO, where RXFIFO == 1'b0, this will be true if the FIFO is not full and so something may be written to the FIFO.

Alternatively, bits [11:2] contain the number of items in the FIFO. You can use those as well to check if the FIFO is full. In other words, when ((status & 0xffc) == 0xffc) you also know that the FIFO is full.

[adumont]

df9ecc0 seems to fix the problem.