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Maybe is not the right way to ask this.
I'm working on a TFG(in spanish), final degree thesis in Computers Engineering in UPM,Madrid,Spain. I had found this repository with an interesting proyect.
I want to know, if there is any possibility to change some things to work on a Zybo Zynq-7000 FPGA board, is the "oldest" board that my university has. If someone thinks there is possible, I need some help with small things concerning with Verilog and which codes I should modify.
First, why Vivado don't accept .inc files for the 6502 code?
Solved: "wrong path for "`include" to ".inc" files" & "changed ".inc" to ".vh" because don't make any difference".
Maybe is not the right way to ask this.
I'm working on a TFG(in spanish), final degree thesis in Computers Engineering in UPM,Madrid,Spain. I had found this repository with an interesting proyect.
I want to know, if there is any possibility to change some things to work on a Zybo Zynq-7000 FPGA board, is the "oldest" board that my university has. If someone thinks there is possible, I need some help with small things concerning with Verilog and which codes I should modify.
First, why Vivado don't accept .inc files for the 6502 code?
Solved: "wrong path for "`include" to ".inc" files" & "changed ".inc" to ".vh" because don't make any difference".
Thanks,
Oskar
Contact: oa.stepien@gmail.com
PS. Maybe I had some mystakes on my English, sorry.
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