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The Verilog files in this directory result from running Yosys [1] to convert the AOKI benchmarks [2] to a flattened gate-level Verilog netlist. | ||
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The files are named according to the schemata: | ||
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SIZE-STAGE1_STAGE2_STAGE3 | ||
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SIZE: Input bit size of multiplier (16bit means that the design multiplies two 16bit numbers, i.e. 16*16) | ||
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STAGE1: The type of first multiplier stage (partial product generator) | ||
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SP: unsigned simple partial product generator | ||
BP: unsigned Booth partial product generator | ||
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STAGE2: The type of second multiplier stage (partial product accumulator) | ||
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AR: Array | ||
CT: Compressor tree | ||
DT: Dadda tree | ||
WT: Wallace tree | ||
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STAGE3: The type of third multiplier stage (final stage adder) | ||
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RC: Ripple carry adder | ||
BK: Brent-Kung adder | ||
LF: Lander-Fischer adder | ||
CL: Carry look-ahead adder | ||
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References: | ||
[1] Clifford Wolf. Yosys open synthesis suite. http://www.clifford.at/yosys/ | ||
[2] Arithmetic module generator based on acg. http://www.aoki.ecei.tohoku.ac.jp/arith/ |
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The Verilog files in this directory have been synthesized by Yosys [1]. | ||
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References: | ||
[1] Clifford Wolf. Yosys open synthesis suite. http://www.clifford.at/yosys/ |