nmigen.lib: Add RoundRobin

nmigen/compat/genlib/roundrobin.py

@@ -0,0 +1,22 @@
+from ..._utils import deprecated
+from ...lib.roundrobin import RoundRobin as NativeRoundRobin
+
+
+__all__ = ["RoundRobin", "SP_WITHDRAW", "SP_CE"]
+
+(SP_WITHDRAW, SP_CE) = range(2)
+
+@deprecated("instead of `migen.genlib.roundrobin.RoundRobin`, "
+            "use `nmigen.lib.roundrobin.RoundRobin`; note that RoundRobin does not "
+            "require a policy anymore, and that the `ce` attribute has been renamed"
+            "to `en`")
+class CompatRoundRobin(NativeRoundRobin):
+    def __init__(self, n, switching_policy=SP_WITHDRAW):
+        super().__init__(n)
+
+        if switching_policy == SP_CE:
+        	self.ce = Signal()
+        	self.comb += self.en.eq(self.ce)
+
+
+RoundRobin = CompatRoundRobin

nmigen/lib/roundrobin.py

@@ -0,0 +1,28 @@
+from .. import *
+
+
+__all__ = ["RoundRobin"]
+
+
+class RoundRobin(Elaboratable):
+    def __init__(self, n):
+        self.requests = Signal(n)
+        self.grant = Signal(range(n))
+        self.en = Signal(reset=1)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        n = self.requests.width
+
+        with m.Switch(self.grant):
+            for i in range(n):
+                with m.Case(i):
+                    for pred in reversed(range(i)):
+                        with m.If(self.requests[pred]):
+                            m.d.sync += self.grant.eq(pred)
+                    for succ in reversed(range(i + 1, n)):
+                        with m.If(self.requests[succ]):
+                            m.d.sync += self.grant.eq(succ)
+
+        return EnableInserter(self.en)(m)

nmigen/test/test_lib_roundrobin.py

@@ -0,0 +1,54 @@
+from .utils import *
+from ..hdl import *
+from ..asserts import *
+from ..sim.pysim import *
+from ..lib.roundrobin import *
+
+class RoundRobinIndividualSpec(Elaboratable):
+    def __init__(self, n):
+        self.n = n
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.submodules.dut = dut = RoundRobin(self.n)
+
+        for i in range(self.n):
+            m.d.sync += Assert((Past(dut.requests) == (1 << i)).implies(dut.grant == i))
+
+        return m
+
+class RoundRobinTestCase(FHDLTestCase):
+    def test_individual(self):
+        self.assertFormal(RoundRobinIndividualSpec(1))
+        self.assertFormal(RoundRobinIndividualSpec(10))
+
+    def test_transitions(self):
+        m = Module()
+        m.submodules.dut = dut = RoundRobin(3)
+
+        sim = Simulator(m)
+        def process():
+            yield dut.requests.eq(0b11)
+            yield Tick(); yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 1)
+
+            yield dut.requests.eq(0b01)
+            yield Tick(); yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 0)
+
+            yield dut.requests.eq(0b01)
+            yield Tick(); yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 0)
+
+            yield dut.requests.eq(0b10)
+            yield Tick(); yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 1)
+
+            yield dut.requests.eq(0b01)
+            yield Tick(); yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 0)
+        sim.add_process(process)
+        sim.add_clock(1e-6)
+        with sim.write_vcd("test.vcd"):
+            sim.run()