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Asynchronous-FIFO
Asynchronous-FIFO PublicRTL of a parametrized asynchronous FIFO that allows for variable depth, data width, and includes almost empty/full flags.
Verilog 6
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OV7670-camera
OV7670-camera PublicA RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 x 480 resolution, 30 fps.
Verilog 5
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OV7670-Video-Processing
OV7670-Video-Processing PublicPipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board
Verilog 2
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CoinCollector-FPGA-game
CoinCollector-FPGA-game PublicFinal Project for ECE 3300: Digital Logic Design Using Verilog.
Verilog
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