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util_axis_fifo_asym: Updated copyright year
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Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
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IstvanZsSzekely committed Mar 8, 2024
1 parent 943376a commit f0e0fd8
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2 changes: 1 addition & 1 deletion library/data_offload/data_offload.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
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2 changes: 1 addition & 1 deletion library/util_axis_fifo_asym/util_axis_fifo_asym.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
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2 changes: 1 addition & 1 deletion library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl
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###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

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